A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs

Cho, Shenghsun; Patel, Mrunal; Kaladagi, Basavaraj; Chen, Han; Palit, Tapti; Ferdman, Michael; Milder, Peter

by Shenghsun Cho, Mrunal Patel, Basavaraj Kaladagi, Han Chen, Tapti Palit, Michael Ferdman, Peter Milder

Reference:

A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs Shenghsun Cho, Mrunal Patel, Basavaraj Kaladagi, Han Chen, Tapti Palit, Michael Ferdman, Peter Milder, Technical report #839, Stony Brook CEAS, 2017.

Bibtex Entry:

@techreport{ferdman-techreport-vm-hdl-co-simulation-framework-for-systems-with-pcie-connected-fpgas,
 author = {Shenghsun Cho and Mrunal Patel and Basavaraj Kaladagi and Han Chen and Tapti Palit and Michael Ferdman and Peter Milder},
 title = {A {VM}-{HDL} {C}o-{S}imulation {F}ramework for {S}ystems with {PCI}e-{C}onnected {FPGA}s},
 year = {2017},
 month = {August},
 institution = {Stony Brook CEAS},
 number = {839},
 pdf = {http://compas.cs.stonybrook.edu/%7Emferdman/downloads.php/TR839_A_VM-HDL_Co-Simulation_Framework_for_Systems_with_PCIe-Connected_FPGAs.pdf},
}