---

hbm_0

altera_hbm v19.6.1

Parameters PHY_DEFAULT_REF_CLK_FREQ false PHY_MEM_CLK_FREQ_MHZ 800.0 PHY_CORE_CLK_FREQ_MHZ 350.0 PHY_HBM_LOCATION TOP PHY_USER_REF_CLK_FREQ_MHZ 100.0 PHY_DEFAULT_CORE_REF_CLK_FREQ false PHY_USER_CORE_REF_CLK_FREQ_MHZ 125.0 PHY_THROTTLE_RDATA_BRESP true PHY_BACKPRESSURE_LATENCY CYCLE_2 PHY_PLACE_BACKPRESSURE_REGS true PHY_TEMP_THROTTLE_THRESHOLD 85 PHY_TEMP_THROTTLE_RATIO 50 PHY_RESET_DEBOUNCE_EN false PHY_AXI_SWITCH_LOGICLOCK false PHY_FPGA_SPEEDGRADE_GUI E2 (Production) - change device under 'View'->'Device Family' PHY_HBM_DEVICE HBM_DEVICE_4GB_4HI CTRL_CH0_CLONE_OF_ID_STR None CTRL_CH0_AVMM_PRECHARGE_EN false CTRL_CH0_AVMM_CMD_PRIOR_CTRL_EN false CTRL_CH0_BL_ADVC_EN false CTRL_CH0_BL_ADVC_VAL 3 CTRL_CH0_INTERFACE AXI4 HARD_CTRL_CH0_CFG_TR_ORDER true HARD_CTRL_CH0_CFG_ADDR_ORDER BGRBC HARD_CTRL_CH0_CFG_USER_RD_AP_POL RDAP_HINT HARD_CTRL_CH0_CFG_USER_WR_AP_POL WRAP_HINT HARD_CTRL_CH0_RFSH_MODE RFSH_MODE_CTRL_RFSH_ALL HARD_CTRL_CH0_CFG_USER_DATA_WIDTH B256 HARD_CTRL_CH0_CFG_MECC_EN false HARD_CTRL_CH0_CFG_WR_DM_EN true HARD_CTRL_CH0_CFG_POWER_DOWN_EN true HARD_CTRL_CH0_CFG_PSEUDO_BL8_EN false HARD_CTRL_CH0_CFG_THROTTLE_EN true CTRL_CH1_CLONE_OF_ID_STR Controller 0 CTRL_CH2_CLONE_OF_ID_STR Controller 0 CTRL_CH3_CLONE_OF_ID_STR Controller 0 CTRL_CH4_CLONE_OF_ID_STR Controller 0 CTRL_CH5_CLONE_OF_ID_STR Controller 0 CTRL_CH6_CLONE_OF_ID_STR Controller 0 CTRL_CH7_CLONE_OF_ID_STR Controller 0 DIAG_RUN_DEFAULT_PATTERN true DIAG_RUN_USER_STAGE false DIAG_FORCE_GENERATE_RW_IDS false DIAG_EFFICIENCY_MONITOR false DIAG_MIXED_TRAFFIC false DIAG_EX_DESIGN_ISSP_EN false DIAG_TG_EXPORT_CFG_INTERFACE false TG_CFG_EN false DIAG_TG_READ_COUNT 5000 DIAG_TG_WRITE_COUNT 2500 DIAG_TG_SEQUENCE TG_SEQUENCE_RANDOM TG_USE_EFFICIENCY_PATTERN false DIAG_TG_EFF_DATA_CHECK_EN true DIAG_MEM_VERBOSE_DIS false DIAG_RW_DATA_MONITOR false PHY_HBM_USER_PLL_REF_CLK_IO_STD_ENUM LVDS_NO_ONCHIP_TERMINATION EX_DESIGN_GUI_GEN_SIM false EX_DESIGN_GUI_GEN_SYNTH true EX_DESIGN_GUI_HDL_FORMAT HDL_FORMAT_VERILOG deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

hbm_0_uib

altera_abstract_uib v19.1

Parameters PORT_MEM_C_WIDTH 8 PORT_MEM_R_WIDTH 6 PORT_MEM_DQ_WIDTH 128 PORT_MEM_DM_WIDTH 16 PORT_MEM_DBI_WIDTH 16 PORT_MEM_PAR_WIDTH 4 PORT_MEM_DERR_WIDTH 4 PORT_MEM_RDQS_T_WIDTH 4 PORT_MEM_RDQS_C_WIDTH 4 PORT_MEM_WDQS_T_WIDTH 4 PORT_MEM_WDQS_C_WIDTH 4 PORT_MEM_RD_WIDTH 8 PORT_M2U_BRIDGE_TEMP_WIDTH 3 PORT_M2U_BRIDGE_WSO_WIDTH 8 PORT_MID_STACK_UFI_TEMP_WIDTH 3 PORT_MID_STACK_UFI_WSO_WIDTH 8 PORT_UB48_RDEN_WIDTH 2 PORT_UB48_RD_VLD_WIDTH 2 PORT_UB48_REMAP_STS_WIDTH 4 PORT_UB48_GROUP_SDOUT0_WIDTH 80 PORT_UB48_GROUP_SDOUT0_EN_WIDTH 2 PORT_UB48_GROUP_SDIN0_WIDTH 80 PORT_UB48_GROUP_SDIN0_EN_WIDTH 2 PORT_UB48_GROUP_DDOUT0_WIDTH 8 PORT_UB48_GROUP_DDOUT0_EN_WIDTH 2 PORT_UB48_GROUP_DDIN0_WIDTH 8 PORT_UB48_GROUP_DDIN0_EN_WIDTH 2 PORT_UB48_GROUP_DDOUT1_WIDTH 8 PORT_UB48_GROUP_DDOUT1_EN_WIDTH 2 PORT_UB48_GROUP_DDIN1_WIDTH 8 PORT_UB48_GROUP_DDIN1_EN_WIDTH 2 PORT_UFI_AXI_EXTRA_AXDOUT0_P0_WIDTH 30 PORT_UFI_AXI_EXTRA_AXDOUT0_P1_WIDTH 20 PORT_UFI_AXI_EXTRA_AXDOUT1_P0_WIDTH 30 PORT_UFI_AXI_EXTRA_AXDOUT1_P1_WIDTH 20 PORT_UFI_AXI_EXTRA_ARDOUT1_P0_WIDTH 50 PORT_UFI_AXI_EXTRA_ARDOUT1_P1_WIDTH 18 PORT_UFI_AXI_EXTRA_ARDOUT1_QOS_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT1_AP_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT1_VLD_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT3_P0_WIDTH 50 PORT_UFI_AXI_EXTRA_ARDOUT3_P1_WIDTH 18 PORT_UFI_AXI_EXTRA_ARDOUT3_QOS_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT3_AP_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT3_VLD_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT0_P0_WIDTH 50 PORT_UFI_AXI_EXTRA_ARDOUT0_P1_WIDTH 18 PORT_UFI_AXI_EXTRA_ARDOUT0_QOS_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT0_AP_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT2_P0_WIDTH 50 PORT_UFI_AXI_EXTRA_ARDOUT2_P1_WIDTH 18 PORT_UFI_AXI_EXTRA_ARDOUT2_AP_WIDTH 2 PORT_UFI_AXI_EXTRA_ARDOUT2_QOS_WIDTH 2 PORT_CAL_LAT_P_WIDTH 3 PORT_F2C_SLAVE_ADDRESS_WIDTH 27 PORT_F2C_SLAVE_RDATA_WIDTH 32 PORT_F2C_SLAVE_WDATA_WIDTH 32 PORT_F2C_SLAVE_BYTEENABLE_WIDTH 4 MEGAFUNC_DEVICE_FAMILY MEM_IF_CLK_MHZ 800 PHYCLK_FREQ_PS 1250 WMCCLK_FREQ_PS 2500 HR_WUFI 1 TXDBI_EN 255 RXDBI_EN 255 TXPAR_EN 255 RXPAR_EN 255 PAR_MODE 65535 PAR_LAT 1 WR_DM_EN 255 RD_DM_EN 0 ECC_DEC_EN 0 ECC_ENC_EN 0 UFI_TOP 1 UIB_FLIPPED 1 PLL_CPA_ONLY_MODE 0 PHY_USE_HARD_CONTROLLER 1 SKIP_CAL 0 EXPORT_DFT 0 SILICON_REV 14nm4b PROT_MODE HBM2 HBMC_MODE hbmc ENABLE_C2F 0 CORE_CLK_FREQ_MHZ 350 DEBOUNCE_PERIOD_MS 20 SEQ_SIM_CAL_CLK_DIVIDE 20 SEQ_SYNTH_CAL_CLK_DIVIDE 30 SEQ_SIM_NIOS_PERIOD_PS 1000 PA_FEEDBACK_DIVIDER_C0 div_by_4 PA_FEEDBACK_DIVIDER_C1 div_by_2 PA_FEEDBACK_DIVIDER_P0 div_by_2 PA_FEEDBACK_DIVIDER_P1 div_by_2 PA_EXPONENT0 7 PA_EXPONENT1 0 PLL_VCO_FREQ_MHZ_INT 800 PLL_VCO_TO_MEM_CLK_FREQ_RATIO 1 PLL_PHY_CLK_VCO_PHASE 0 PLL_NCNTR_SETTING 1 PLL_VCO_FREQ_PS_STR 1250 ps PLL_REF_CLK_FREQ_PS_STR 10000 ps PLL_SIM_VCO_FREQ_PS 1244 PLL_SIM_PHYCLK_0_FREQ_PS 3732 PLL_SIM_PHYCLK_1_FREQ_PS 1244 PLL_SIM_PHY_CLK_VCO_PHASE_PS 0 PLL_REF_CLK_FREQ_PS_STR_FROM_API 10000 ps PLL_VCO_FREQ_PS_STR_FROM_API 1250 ps PLL_M_CNT_HIGH 4 PLL_M_CNT_LOW 4 PLL_N_CNT_HIGH 256 PLL_N_CNT_LOW 256 PLL_M_CNT_BYPASS_EN false PLL_N_CNT_BYPASS_EN true PLL_M_CNT_EVEN_DUTY_EN false PLL_N_CNT_EVEN_DUTY_EN false PLL_CP_SETTING pll_cp_setting10 PLL_RIPPLECAP_SETTING pll_ripplecap_setting0 PLL_BW_CTRL pll_bw_res_setting3 PLL_C_CNT_HIGH_0 256 PLL_C_CNT_LOW_0 256 PLL_C_CNT_PRST_0 1 PLL_C_CNT_PH_MUX_PRST_0 0 PLL_C_CNT_BYPASS_EN_0 true PLL_C_CNT_EVEN_DUTY_EN_0 false PLL_C_CNT_HIGH_1 2 PLL_C_CNT_LOW_1 1 PLL_C_CNT_PRST_1 1 PLL_C_CNT_PH_MUX_PRST_1 0 PLL_C_CNT_BYPASS_EN_1 false PLL_C_CNT_EVEN_DUTY_EN_1 true PLL_C_CNT_HIGH_2 256 PLL_C_CNT_LOW_2 256 PLL_C_CNT_PRST_2 1 PLL_C_CNT_PH_MUX_PRST_2 0 PLL_C_CNT_BYPASS_EN_2 true PLL_C_CNT_EVEN_DUTY_EN_2 false PLL_C_CNT_HIGH_3 256 PLL_C_CNT_LOW_3 256 PLL_C_CNT_PRST_3 1 PLL_C_CNT_PH_MUX_PRST_3 0 PLL_C_CNT_BYPASS_EN_3 true PLL_C_CNT_EVEN_DUTY_EN_3 false PLL_C_CNT_HIGH_4 256 PLL_C_CNT_LOW_4 256 PLL_C_CNT_PRST_4 1 PLL_C_CNT_PH_MUX_PRST_4 0 PLL_C_CNT_BYPASS_EN_4 true PLL_C_CNT_EVEN_DUTY_EN_4 false PLL_C_CNT_HIGH_5 256 PLL_C_CNT_LOW_5 256 PLL_C_CNT_PRST_5 1 PLL_C_CNT_PH_MUX_PRST_5 0 PLL_C_CNT_BYPASS_EN_5 true PLL_C_CNT_EVEN_DUTY_EN_5 false PLL_C_CNT_HIGH_6 256 PLL_C_CNT_LOW_6 256 PLL_C_CNT_PRST_6 1 PLL_C_CNT_PH_MUX_PRST_6 0 PLL_C_CNT_BYPASS_EN_6 true PLL_C_CNT_EVEN_DUTY_EN_6 false PLL_C_CNT_HIGH_7 256 PLL_C_CNT_LOW_7 256 PLL_C_CNT_PRST_7 1 PLL_C_CNT_PH_MUX_PRST_7 0 PLL_C_CNT_BYPASS_EN_7 true PLL_C_CNT_EVEN_DUTY_EN_7 false PLL_C_CNT_HIGH_8 256 PLL_C_CNT_LOW_8 256 PLL_C_CNT_PRST_8 1 PLL_C_CNT_PH_MUX_PRST_8 0 PLL_C_CNT_BYPASS_EN_8 true PLL_C_CNT_EVEN_DUTY_EN_8 false PLL_C_CNT_FREQ_PS_STR_0 1250 ps PLL_C_CNT_PHASE_PS_STR_0 0 ps PLL_C_CNT_DUTY_CYCLE_0 50 PLL_C_CNT_FREQ_PS_STR_1 3750 ps PLL_C_CNT_PHASE_PS_STR_1 0 ps PLL_C_CNT_DUTY_CYCLE_1 50 PLL_C_CNT_FREQ_PS_STR_2 0.0 MHz PLL_C_CNT_PHASE_PS_STR_2 0 ps PLL_C_CNT_DUTY_CYCLE_2 50 PLL_C_CNT_FREQ_PS_STR_3 0.0 MHz PLL_C_CNT_PHASE_PS_STR_3 0 ps PLL_C_CNT_DUTY_CYCLE_3 50 PLL_C_CNT_FREQ_PS_STR_4 0.0 MHz PLL_C_CNT_PHASE_PS_STR_4 0 ps PLL_C_CNT_DUTY_CYCLE_4 50 PLL_C_CNT_FREQ_PS_STR_5 0.0 MHz PLL_C_CNT_PHASE_PS_STR_5 0 ps PLL_C_CNT_DUTY_CYCLE_5 50 PLL_C_CNT_FREQ_PS_STR_6 0.0 MHz PLL_C_CNT_PHASE_PS_STR_6 0 ps PLL_C_CNT_DUTY_CYCLE_6 50 PLL_C_CNT_FREQ_PS_STR_7 0.0 MHz PLL_C_CNT_PHASE_PS_STR_7 0 ps PLL_C_CNT_DUTY_CYCLE_7 50 PLL_C_CNT_FREQ_PS_STR_8 0.0 MHz PLL_C_CNT_PHASE_PS_STR_8 0 ps PLL_C_CNT_DUTY_CYCLE_8 50 PLL_C_CNT_OUT_EN_0 true PLL_C_CNT_OUT_EN_1 true PLL_C_CNT_OUT_EN_2 false PLL_C_CNT_OUT_EN_3 false PLL_C_CNT_OUT_EN_4 false PLL_C_CNT_OUT_EN_5 false PLL_C_CNT_OUT_EN_6 false PLL_C_CNT_OUT_EN_7 false PLL_C_CNT_OUT_EN_8 false PLL_FBCLK_MUX_1 pll_fbclk_mux_1_glb PLL_FBCLK_MUX_2 pll_fbclk_mux_2_m_cnt PLL_M_CNT_IN_SRC c_m_cnt_in_src_ph_mux_clk PLL_BW_SEL high HBMC_CH0_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH0_HBM_TRRDL 4 HBMC_CH0_HBM_TRCDRD 12 HBMC_CH0_HBM_TRCDWR 8 HBMC_CH0_HBM_TRTPL_BL4 5 HBMC_CH0_HBM_TRTPS_BL4 4 HBMC_CH0_HBM_TRP 12 HBMC_CH0_HBM_TCCDS_BL4 2 HBMC_CH0_HBM_TCCDR 3 HBMC_CH0_HBM_TWR 13 HBMC_CH0_HBM_TWTRL 7 HBMC_CH0_HBM_TWTRS 3 HBMC_CH0_HBM_TDQSS_MAX_PS 200 HBMC_CH0_HBM_TDQSS_MIN_PS 200 HBMC_CH0_HBM_TDQSCK_MAX_PS 3500 HBMC_CH0_HBM_TDQSQ_MAX_PS 105 HBMC_CH0_HBM_PARAM_TYPE hbm_param_min HBMC_CH0_RFSH_POLICY rfsh_policy_flexible HBMC_CH0_HBM_TREFI 3120 HBMC_CH0_HBM_TCKSRE 8 HBMC_CH0_HBM_TCKSRX 8 HBMC_CH0_HBM_TXS 216 HBMC_CH0_HBM_TCKESR 7 HBMC_CH0_HBM_TXP 6 HBMC_CH0_HBM_TPD 6 HBMC_CH0_CFG_HBMC_MODES prod HBMC_CH0_CORE_CLOCK_MHZ 350 HBMC_CH0_CORE_CLOCK_PS 1000 HBMC_CH0_CFG_CHANNEL_EN enable HBMC_CH0_CFG_TR_ORDER enable HBMC_CH0_CFG_ADDR_ORDER bgrbc HBMC_CH0_CFG_USER_RD_AP_POL rdap_hint HBMC_CH0_CFG_USER_WR_AP_POL wrap_hint HBMC_CH0_CFG_RID_DEPENDENCY_EN enable HBMC_CH0_CFG_HBMC_TX_BYPASS disable HBMC_CH0_CFG_HBMC_RX_BYPASS disable HBMC_CH0_CFG_P2HPEMUEN 0 HBMC_CH0_CFG_RMPTREN disable HBMC_CH0_CFG_RMPTRENDLY00 1 HBMC_CH0_CFG_RMPTRENDLY01 2 HBMC_CH0_CFG_RMPTRENDLY02 3 HBMC_CH0_CFG_RMPTRENDLY03 4 HBMC_CH0_CFG_RMPTRENDLY04 5 HBMC_CH0_HBM_TRAS 27 HBMC_CH0_HBM_TRRDS 4 HBMC_CH0_HBMC_OFFSET 1 HBMC_CH0_HBMC_RATE_VALUE rate_half HBMC_CH0_HBM_CLOCK_MHZ 800 HBMC_CH0_HBM_CLOCK_PS 1250 HBMC_CH0_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH0_HBM_TRFC 208 HBMC_CH0_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH0_EXT_RDIE 2 HBMC_CH0_TEMP000_THROTTLE_RATIO 0 HBMC_CH0_TEMP001_THROTTLE_RATIO 0 HBMC_CH0_TEMP010_THROTTLE_RATIO 50 HBMC_CH0_TEMP011_THROTTLE_RATIO 0 HBMC_CH0_TEMP100_THROTTLE_RATIO 0 HBMC_CH0_TEMP101_THROTTLE_RATIO 0 HBMC_CH0_TEMP110_THROTTLE_RATIO 50 HBMC_CH0_TEMP111_THROTTLE_RATIO 50 HBMC_CH0_CORE_CLK_MODE hr_asyn HBMC_CH0_CFG_HBMC_BL 4 HBMC_CH0_USER_STRB_EN enable HBMC_CH0_CFG_TBHMCRSTMIN 0 HBMC_CH0_CFG_RESET_COUNT 0 HBMC_CH0_CFG_HBMC_PC0_WL 6 HBMC_CH0_CFG_HBMC_PC0_RL 18 HBMC_CH0_CFG_HBMC_PC1_WL 6 HBMC_CH0_CFG_HBMC_PC1_RL 18 HBMC_CH0_CFG_POSTCAL_STATE sr HBMC_CH0_CFG_UFIC2PDLY 0 HBMC_CH0_CFG_UFIP2CDLY 0 HBMC_CH0_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH0_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH0_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH0_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH0_CFG_HBMC_PC0_SCR_EN enable HBMC_CH0_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH0_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH0_CFG_HBMC_PC1_SCR_EN enable HBMC_CH0_CFG_FLIP_MODE enable HBMC_CH0_CFG_DENSITY 1 HBMC_CH0_CFG_USER_DATA_WIDTH b256 HBMC_CH0_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH0_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH0_CFG_CB_RVALID_GATE_EN enable HBMC_CH0_CFG_CB_BVALID_GATE_EN enable HBMC_CH0_CFG_ADDRCHNLMUXEN disable HBMC_CH0_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH0_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH0_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH0_CFG_RCQ_AGE_LIMIT 32 HBMC_CH0_CFG_RDB_RSVD_ENTRY 0 HBMC_CH0_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH0_CFG_PC0_CMD2RDEN 15 HBMC_CH0_CFG_PC1_CMD2RDEN 16 HBMC_CH0_CFG_PC0_CMD2RDIE 13 HBMC_CH0_CFG_PC1_CMD2RDIE 14 HBMC_CH0_CFG_PC0_DATAOE_ON 2 HBMC_CH0_CFG_PC1_DATAOE_ON 2 HBMC_CH0_CFG_PC0_CMD2DATA 3 HBMC_CH0_CFG_PC1_CMD2DATA 4 HBMC_CH0_CFG_WDB_RSVD_ENTRY 32 HBMC_CH0_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH0_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH0_CFG_WCQ_LWM 8 HBMC_CH0_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH0_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH0_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH0_CFG_PC0_CMD2WDQS 2 HBMC_CH0_CFG_PC1_CMD2WDQS 3 HBMC_CH0_CFG_PC0_CMD2DATAOE 3 HBMC_CH0_CFG_PC1_CMD2DATAOE 4 HBMC_CH0_CFG_CB_MAJOR_MODE_EN enable HBMC_CH0_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH0_CFG_RFSH_ALL_EN enable HBMC_CH0_CFG_RFSH_PB_EN disable HBMC_CH0_CFG_USER_RFSH_PB_EN enable HBMC_CH0_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH0_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH0_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH0_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH0_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH0_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH0_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH0_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH0_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH0_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH0_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH0_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH0_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH0_CFG_TEMP_FILTER_EN enable HBMC_CH0_CFG_CATTRIP_FILTER_EN enable HBMC_CH0_CFG_CB_BYPASS_CATTRIP disable HBMC_CH0_CFG_CB_TEMP_SELECT disable HBMC_CH0_CFG_F2C_TEMP_UPDATE disable HBMC_CH0_CFG_F2C_TEMP 3 HBMC_CH0_CFG_ADDR_SCR none HBMC_CH0_CFG_ADDR_SPRD disable HBMC_CH0_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH0_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH0_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH0_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH0_CFG_CB_DEPENDENCY_MODE enable HBMC_CH0_CFG_MECC_EN disable HBMC_CH0_CFG_CA_PAR_EN enable HBMC_CH0_CFG_WR_PAR_EN enable HBMC_CH0_CFG_RD_PAR_EN enable HBMC_CH0_CFG_WR_DM_EN enable HBMC_CH0_CFG_RD_DM_EN disable HBMC_CH0_CFG_POWER_DOWN_EN enable HBMC_CH0_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH0_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH0_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH0_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH0_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH0_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH0_CFG_SELF_RFSH_EN enable HBMC_CH0_H0_FR_CLK_STCFG_EN disable HBMC_CH0_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH0_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH0_CFG_HBMC_CORECLK_PROG_DELAY1 8191 HBMC_CH0_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH0_CFG_HBMCPTRENSYNCSEL enable HBMC_CH0_CFG_UB48MODE enable HBMC_CH0_CFG_HBMCH2CPTRSTART 6 HBMC_CH0_CFG_DWORD_LPBKEN disable HBMC_CH0_CFG_AWORD_LPBEN disable HBMC_CH0_CFG_DWORD_LPBKSEL disable HBMC_CH0_CFG_AWORD_LPBKSEL 0 HBMC_CH0_CFG_OBSGRPSEL 0 HBMC_CH0_CFG_OBSSIGSEL 0 HBMC_CH0_CFG_MEM_MCE disable HBMC_CH0_CFG_MEM_WA 6 HBMC_CH0_CFG_MEM_RMCE 1 HBMC_CH0_CFG_MEM_WMCE 1 HBMC_CH0_CFG_MEM_WPULSE 2 HBMC_CH0_CFG_SRAM_ECC_ENABLE enable HBMC_CH0_CFG_PC0_SRAM_INJD disable HBMC_CH0_CFG_PC0_SRAM_INJS disable HBMC_CH0_CFG_PC1_SRAM_INJD disable HBMC_CH0_CFG_PC1_SRAM_INJS disable HBMC_CH0_CFG_SRAM_SERRINTEN enable HBMC_CH0_CFG_SRAM_SLVERR_DIS disable HBMC_CH0_MMR_USER_TRIGGER disable HBMC_CH0_MMR_USER_RDWR disable HBMC_CH0_MMR_USER_BYTEENABLE 0 HBMC_CH0_MMR_USER_ADDR 0 HBMC_CH0_MMR_USER_WRDATA 0 HBMC_CH0_MMR_SBOWN_REQ disable HBMC_CH0_MMR_SBOWN_DELAY 100 HBMC_CH0_CFG_SKETCH1 3 HBMC_CH0_CFG_SKETCH2 0 HBMC_CH0_CFG_TST_PATTERN 0 HBMC_CH0_CFG_TST_START_ADDR 0 HBMC_CH0_CFG_TST_BURST_LEN 0 HBMC_CH0_CFG_TST_GEN_CMD 0 HBMC_CH0_CFG_AXI_TRAFFIC_SEL disable HBMC_CH0_CFG_TST_PC_SEL disable HBMC_CH0_CFG_TST_TRIGGER disable HBMC_CH0_CFG_TST_TIME_OUT 0 HBMC_CH0_HBMC_RATE 2 HBMC_CH0_HBM_TRFCSB 128 HBMC_CH0_HBM_TRREFD 7 HBMC_CH0_UFI_TRDEN 23 HBMC_CH0_CFG_HBMC_PC0_WTP 10 HBMC_CH0_CFG_HBMC_PC1_WTP 10 HBMC_CH0_CFG_HBMC_PC0_ITP 19 HBMC_CH0_CFG_HBMC_PC1_ITP 19 HBMC_CH0_CFG_HBMC_PC0_RTP 2 HBMC_CH0_CFG_HBMC_PC1_RTP 2 HBMC_CH0_CFG_PAR_LAT 1 HBMC_CH0_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH0_CFG_HBMC_PC0_ATI 13 HBMC_CH0_CFG_HBMC_PC0_ITI 19 HBMC_CH0_CFG_HBMC_PC0_ATA 19 HBMC_CH0_CFG_HBMC_PC0_ITA 25 HBMC_CH0_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH0_CFG_HBMC_PC0_ATP 13 HBMC_CH0_CFG_HBMC_PC0_ATR 6 HBMC_CH0_CFG_HBMC_PC0_ITR 12 HBMC_CH0_CFG_HBMC_PC0_ATW 5 HBMC_CH0_CFG_HBMC_PC0_ITW 10 HBMC_CH0_CFG_HBMC_PC0_PTA 5 HBMC_CH0_CFG_HBMC_PC0_WTI 9 HBMC_CH0_CFG_HBMC_PC0_RTA 7 HBMC_CH0_CFG_HBMC_PC0_WTA 15 HBMC_CH0_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH0_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH0_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH0_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH0_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH0_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH0_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH0_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH0_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH0_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH0_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH0_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH0_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH0_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH0_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH0_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH0_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH0_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH0_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH0_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH0_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH0_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH0_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH0_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH0_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH0_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH0_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH0_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH0_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH0_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH0_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH0_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH0_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH0_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH0_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH0_CFG_HBMC_PC1_ATI 13 HBMC_CH0_CFG_HBMC_PC1_ITI 19 HBMC_CH0_CFG_HBMC_PC1_ATA 19 HBMC_CH0_CFG_HBMC_PC1_ITA 25 HBMC_CH0_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH0_CFG_HBMC_PC1_ATP 13 HBMC_CH0_CFG_HBMC_PC1_ATR 5 HBMC_CH0_CFG_HBMC_PC1_ITR 11 HBMC_CH0_CFG_HBMC_PC1_ATW 5 HBMC_CH0_CFG_HBMC_PC1_ITW 9 HBMC_CH0_CFG_HBMC_PC1_PTA 5 HBMC_CH0_CFG_HBMC_PC1_WTI 10 HBMC_CH0_CFG_HBMC_PC1_RTA 8 HBMC_CH0_CFG_HBMC_PC1_WTA 16 HBMC_CH0_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH0_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH0_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH0_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH0_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH0_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH0_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH0_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH0_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH0_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH0_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH0_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH0_CFG_PSEUDO_BL8_EN disable HBMC_CH0_CFG_CB_WREADY_GATE_EN disable HBMC_CH0_CFG_PC0_RDEN_ON 5 HBMC_CH0_CFG_PC1_RDEN_ON 5 HBMC_CH0_CFG_PC0_RDIE_ON 9 HBMC_CH0_CFG_PC1_RDIE_ON 9 HBMC_CH0_CFG_PC0_CMD2RD 30 HBMC_CH0_CFG_PC1_CMD2RD 31 HBMC_CH0_CFG_PC0_CMD2RDPAR 31 HBMC_CH0_CFG_PC1_CMD2RDPAR 32 HBMC_CH0_CFG_PC0_WDQS_ON 4 HBMC_CH0_CFG_PC1_WDQS_ON 4 HBMC_CH0_CFG_WCQ_HWM 24 HBMC_CH0_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH0_CFG_THROTTLE_EN enable HBMC_CH0_CFG_TEMP000_ON_TIME 0 HBMC_CH0_CFG_TEMP001_ON_TIME 0 HBMC_CH0_CFG_TEMP010_ON_TIME 127 HBMC_CH0_CFG_TEMP011_ON_TIME 0 HBMC_CH0_CFG_TEMP100_ON_TIME 0 HBMC_CH0_CFG_TEMP101_ON_TIME 0 HBMC_CH0_CFG_TEMP110_ON_TIME 127 HBMC_CH0_CFG_TEMP111_ON_TIME 127 HBMC_CH0_CFG_TEMP000_OFF_TIME 255 HBMC_CH0_CFG_TEMP001_OFF_TIME 255 HBMC_CH0_CFG_TEMP010_OFF_TIME 127 HBMC_CH0_CFG_TEMP011_OFF_TIME 255 HBMC_CH0_CFG_TEMP100_OFF_TIME 255 HBMC_CH0_CFG_TEMP101_OFF_TIME 255 HBMC_CH0_CFG_TEMP110_OFF_TIME 127 HBMC_CH0_CFG_TEMP111_OFF_TIME 127 HBMC_CH0_CFG_RMW_EN disable HBMC_CH0_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH0_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH0_CFG_HBMCC2HPTRDLY 0 HBMC_CH0_HBM_TCCDL_BL4 4 HBMC_CH0_HBM_TRTW 15 HBMC_CH0_HBM_TFAW 16 HBMC_CH0_HBM_TEAW 24 HBMC_CH0_CFG_HBMC_PC0_FAW 5 HBMC_CH0_CFG_HBMC_PC0_RTI 1 HBMC_CH0_CFG_HBMC_PC0_RTW 13 HBMC_CH0_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH0_CFG_HBMC_PC1_FAW 5 HBMC_CH0_CFG_HBMC_PC1_RTI 2 HBMC_CH0_CFG_HBMC_PC1_RTW 13 HBMC_CH0_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH0_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH0_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH1_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH1_HBM_TRRDL 4 HBMC_CH1_HBM_TRCDRD 12 HBMC_CH1_HBM_TRCDWR 8 HBMC_CH1_HBM_TRTPL_BL4 5 HBMC_CH1_HBM_TRTPS_BL4 4 HBMC_CH1_HBM_TRP 12 HBMC_CH1_HBM_TCCDS_BL4 2 HBMC_CH1_HBM_TCCDR 3 HBMC_CH1_HBM_TWR 13 HBMC_CH1_HBM_TWTRL 7 HBMC_CH1_HBM_TWTRS 3 HBMC_CH1_HBM_TDQSS_MAX_PS 200 HBMC_CH1_HBM_TDQSS_MIN_PS 200 HBMC_CH1_HBM_TDQSCK_MAX_PS 3500 HBMC_CH1_HBM_TDQSQ_MAX_PS 105 HBMC_CH1_HBM_PARAM_TYPE hbm_param_min HBMC_CH1_RFSH_POLICY rfsh_policy_flexible HBMC_CH1_HBM_TREFI 3120 HBMC_CH1_HBM_TCKSRE 8 HBMC_CH1_HBM_TCKSRX 8 HBMC_CH1_HBM_TXS 216 HBMC_CH1_HBM_TCKESR 7 HBMC_CH1_HBM_TXP 6 HBMC_CH1_HBM_TPD 6 HBMC_CH1_CFG_HBMC_MODES prod HBMC_CH1_CORE_CLOCK_MHZ 350 HBMC_CH1_CORE_CLOCK_PS 1000 HBMC_CH1_CFG_CHANNEL_EN enable HBMC_CH1_CFG_TR_ORDER enable HBMC_CH1_CFG_ADDR_ORDER bgrbc HBMC_CH1_CFG_USER_RD_AP_POL rdap_hint HBMC_CH1_CFG_USER_WR_AP_POL wrap_hint HBMC_CH1_CFG_RID_DEPENDENCY_EN enable HBMC_CH1_CFG_HBMC_TX_BYPASS disable HBMC_CH1_CFG_HBMC_RX_BYPASS disable HBMC_CH1_CFG_P2HPEMUEN 0 HBMC_CH1_CFG_RMPTREN disable HBMC_CH1_CFG_RMPTRENDLY00 1 HBMC_CH1_CFG_RMPTRENDLY01 2 HBMC_CH1_CFG_RMPTRENDLY02 3 HBMC_CH1_CFG_RMPTRENDLY03 4 HBMC_CH1_CFG_RMPTRENDLY04 5 HBMC_CH1_HBM_TRAS 27 HBMC_CH1_HBM_TRRDS 4 HBMC_CH1_HBMC_OFFSET 1 HBMC_CH1_HBMC_RATE_VALUE rate_half HBMC_CH1_HBM_CLOCK_MHZ 800 HBMC_CH1_HBM_CLOCK_PS 1250 HBMC_CH1_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH1_HBM_TRFC 208 HBMC_CH1_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH1_EXT_RDIE 2 HBMC_CH1_TEMP000_THROTTLE_RATIO 0 HBMC_CH1_TEMP001_THROTTLE_RATIO 0 HBMC_CH1_TEMP010_THROTTLE_RATIO 50 HBMC_CH1_TEMP011_THROTTLE_RATIO 0 HBMC_CH1_TEMP100_THROTTLE_RATIO 0 HBMC_CH1_TEMP101_THROTTLE_RATIO 0 HBMC_CH1_TEMP110_THROTTLE_RATIO 50 HBMC_CH1_TEMP111_THROTTLE_RATIO 50 HBMC_CH1_CORE_CLK_MODE hr_asyn HBMC_CH1_CFG_HBMC_BL 4 HBMC_CH1_USER_STRB_EN enable HBMC_CH1_CFG_TBHMCRSTMIN 0 HBMC_CH1_CFG_RESET_COUNT 0 HBMC_CH1_CFG_HBMC_PC0_WL 6 HBMC_CH1_CFG_HBMC_PC0_RL 18 HBMC_CH1_CFG_HBMC_PC1_WL 6 HBMC_CH1_CFG_HBMC_PC1_RL 18 HBMC_CH1_CFG_POSTCAL_STATE sr HBMC_CH1_CFG_UFIC2PDLY 0 HBMC_CH1_CFG_UFIP2CDLY 0 HBMC_CH1_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH1_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH1_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH1_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH1_CFG_HBMC_PC0_SCR_EN enable HBMC_CH1_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH1_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH1_CFG_HBMC_PC1_SCR_EN enable HBMC_CH1_CFG_FLIP_MODE enable HBMC_CH1_CFG_DENSITY 1 HBMC_CH1_CFG_USER_DATA_WIDTH b256 HBMC_CH1_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH1_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH1_CFG_CB_RVALID_GATE_EN enable HBMC_CH1_CFG_CB_BVALID_GATE_EN enable HBMC_CH1_CFG_ADDRCHNLMUXEN disable HBMC_CH1_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH1_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH1_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH1_CFG_RCQ_AGE_LIMIT 32 HBMC_CH1_CFG_RDB_RSVD_ENTRY 0 HBMC_CH1_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH1_CFG_PC0_CMD2RDEN 15 HBMC_CH1_CFG_PC1_CMD2RDEN 16 HBMC_CH1_CFG_PC0_CMD2RDIE 13 HBMC_CH1_CFG_PC1_CMD2RDIE 14 HBMC_CH1_CFG_PC0_DATAOE_ON 2 HBMC_CH1_CFG_PC1_DATAOE_ON 2 HBMC_CH1_CFG_PC0_CMD2DATA 3 HBMC_CH1_CFG_PC1_CMD2DATA 4 HBMC_CH1_CFG_WDB_RSVD_ENTRY 32 HBMC_CH1_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH1_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH1_CFG_WCQ_LWM 8 HBMC_CH1_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH1_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH1_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH1_CFG_PC0_CMD2WDQS 2 HBMC_CH1_CFG_PC1_CMD2WDQS 3 HBMC_CH1_CFG_PC0_CMD2DATAOE 3 HBMC_CH1_CFG_PC1_CMD2DATAOE 4 HBMC_CH1_CFG_CB_MAJOR_MODE_EN enable HBMC_CH1_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH1_CFG_RFSH_ALL_EN enable HBMC_CH1_CFG_RFSH_PB_EN disable HBMC_CH1_CFG_USER_RFSH_PB_EN enable HBMC_CH1_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH1_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH1_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH1_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH1_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH1_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH1_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH1_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH1_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH1_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH1_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH1_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH1_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH1_CFG_TEMP_FILTER_EN enable HBMC_CH1_CFG_CATTRIP_FILTER_EN enable HBMC_CH1_CFG_CB_BYPASS_CATTRIP disable HBMC_CH1_CFG_CB_TEMP_SELECT disable HBMC_CH1_CFG_F2C_TEMP_UPDATE disable HBMC_CH1_CFG_F2C_TEMP 3 HBMC_CH1_CFG_ADDR_SCR none HBMC_CH1_CFG_ADDR_SPRD disable HBMC_CH1_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH1_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH1_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH1_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH1_CFG_CB_DEPENDENCY_MODE enable HBMC_CH1_CFG_MECC_EN disable HBMC_CH1_CFG_CA_PAR_EN enable HBMC_CH1_CFG_WR_PAR_EN enable HBMC_CH1_CFG_RD_PAR_EN enable HBMC_CH1_CFG_WR_DM_EN enable HBMC_CH1_CFG_RD_DM_EN disable HBMC_CH1_CFG_POWER_DOWN_EN enable HBMC_CH1_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH1_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH1_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH1_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH1_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH1_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH1_CFG_SELF_RFSH_EN enable HBMC_CH1_H0_FR_CLK_STCFG_EN disable HBMC_CH1_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH1_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH1_CFG_HBMC_CORECLK_PROG_DELAY1 8191 HBMC_CH1_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH1_CFG_HBMCPTRENSYNCSEL enable HBMC_CH1_CFG_UB48MODE enable HBMC_CH1_CFG_HBMCH2CPTRSTART 6 HBMC_CH1_CFG_DWORD_LPBKEN disable HBMC_CH1_CFG_AWORD_LPBEN disable HBMC_CH1_CFG_DWORD_LPBKSEL disable HBMC_CH1_CFG_AWORD_LPBKSEL 0 HBMC_CH1_CFG_OBSGRPSEL 0 HBMC_CH1_CFG_OBSSIGSEL 0 HBMC_CH1_CFG_MEM_MCE disable HBMC_CH1_CFG_MEM_WA 6 HBMC_CH1_CFG_MEM_RMCE 1 HBMC_CH1_CFG_MEM_WMCE 1 HBMC_CH1_CFG_MEM_WPULSE 2 HBMC_CH1_CFG_SRAM_ECC_ENABLE enable HBMC_CH1_CFG_PC0_SRAM_INJD disable HBMC_CH1_CFG_PC0_SRAM_INJS disable HBMC_CH1_CFG_PC1_SRAM_INJD disable HBMC_CH1_CFG_PC1_SRAM_INJS disable HBMC_CH1_CFG_SRAM_SERRINTEN enable HBMC_CH1_CFG_SRAM_SLVERR_DIS disable HBMC_CH1_MMR_USER_TRIGGER disable HBMC_CH1_MMR_USER_RDWR disable HBMC_CH1_MMR_USER_BYTEENABLE 0 HBMC_CH1_MMR_USER_ADDR 0 HBMC_CH1_MMR_USER_WRDATA 0 HBMC_CH1_MMR_SBOWN_REQ disable HBMC_CH1_MMR_SBOWN_DELAY 100 HBMC_CH1_CFG_SKETCH1 3 HBMC_CH1_CFG_SKETCH2 0 HBMC_CH1_CFG_TST_PATTERN 0 HBMC_CH1_CFG_TST_START_ADDR 0 HBMC_CH1_CFG_TST_BURST_LEN 0 HBMC_CH1_CFG_TST_GEN_CMD 0 HBMC_CH1_CFG_AXI_TRAFFIC_SEL disable HBMC_CH1_CFG_TST_PC_SEL disable HBMC_CH1_CFG_TST_TRIGGER disable HBMC_CH1_CFG_TST_TIME_OUT 0 HBMC_CH1_HBMC_RATE 2 HBMC_CH1_HBM_TRFCSB 128 HBMC_CH1_HBM_TRREFD 7 HBMC_CH1_UFI_TRDEN 23 HBMC_CH1_CFG_HBMC_PC0_WTP 10 HBMC_CH1_CFG_HBMC_PC1_WTP 10 HBMC_CH1_CFG_HBMC_PC0_ITP 19 HBMC_CH1_CFG_HBMC_PC1_ITP 19 HBMC_CH1_CFG_HBMC_PC0_RTP 2 HBMC_CH1_CFG_HBMC_PC1_RTP 2 HBMC_CH1_CFG_PAR_LAT 1 HBMC_CH1_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH1_CFG_HBMC_PC0_ATI 13 HBMC_CH1_CFG_HBMC_PC0_ITI 19 HBMC_CH1_CFG_HBMC_PC0_ATA 19 HBMC_CH1_CFG_HBMC_PC0_ITA 25 HBMC_CH1_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH1_CFG_HBMC_PC0_ATP 13 HBMC_CH1_CFG_HBMC_PC0_ATR 6 HBMC_CH1_CFG_HBMC_PC0_ITR 12 HBMC_CH1_CFG_HBMC_PC0_ATW 5 HBMC_CH1_CFG_HBMC_PC0_ITW 10 HBMC_CH1_CFG_HBMC_PC0_PTA 5 HBMC_CH1_CFG_HBMC_PC0_WTI 9 HBMC_CH1_CFG_HBMC_PC0_RTA 7 HBMC_CH1_CFG_HBMC_PC0_WTA 15 HBMC_CH1_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH1_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH1_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH1_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH1_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH1_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH1_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH1_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH1_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH1_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH1_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH1_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH1_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH1_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH1_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH1_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH1_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH1_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH1_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH1_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH1_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH1_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH1_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH1_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH1_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH1_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH1_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH1_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH1_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH1_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH1_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH1_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH1_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH1_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH1_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH1_CFG_HBMC_PC1_ATI 13 HBMC_CH1_CFG_HBMC_PC1_ITI 19 HBMC_CH1_CFG_HBMC_PC1_ATA 19 HBMC_CH1_CFG_HBMC_PC1_ITA 25 HBMC_CH1_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH1_CFG_HBMC_PC1_ATP 13 HBMC_CH1_CFG_HBMC_PC1_ATR 5 HBMC_CH1_CFG_HBMC_PC1_ITR 11 HBMC_CH1_CFG_HBMC_PC1_ATW 5 HBMC_CH1_CFG_HBMC_PC1_ITW 9 HBMC_CH1_CFG_HBMC_PC1_PTA 5 HBMC_CH1_CFG_HBMC_PC1_WTI 10 HBMC_CH1_CFG_HBMC_PC1_RTA 8 HBMC_CH1_CFG_HBMC_PC1_WTA 16 HBMC_CH1_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH1_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH1_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH1_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH1_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH1_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH1_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH1_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH1_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH1_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH1_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH1_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH1_CFG_PSEUDO_BL8_EN disable HBMC_CH1_CFG_CB_WREADY_GATE_EN disable HBMC_CH1_CFG_PC0_RDEN_ON 5 HBMC_CH1_CFG_PC1_RDEN_ON 5 HBMC_CH1_CFG_PC0_RDIE_ON 9 HBMC_CH1_CFG_PC1_RDIE_ON 9 HBMC_CH1_CFG_PC0_CMD2RD 30 HBMC_CH1_CFG_PC1_CMD2RD 31 HBMC_CH1_CFG_PC0_CMD2RDPAR 31 HBMC_CH1_CFG_PC1_CMD2RDPAR 32 HBMC_CH1_CFG_PC0_WDQS_ON 4 HBMC_CH1_CFG_PC1_WDQS_ON 4 HBMC_CH1_CFG_WCQ_HWM 24 HBMC_CH1_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH1_CFG_THROTTLE_EN enable HBMC_CH1_CFG_TEMP000_ON_TIME 0 HBMC_CH1_CFG_TEMP001_ON_TIME 0 HBMC_CH1_CFG_TEMP010_ON_TIME 127 HBMC_CH1_CFG_TEMP011_ON_TIME 0 HBMC_CH1_CFG_TEMP100_ON_TIME 0 HBMC_CH1_CFG_TEMP101_ON_TIME 0 HBMC_CH1_CFG_TEMP110_ON_TIME 127 HBMC_CH1_CFG_TEMP111_ON_TIME 127 HBMC_CH1_CFG_TEMP000_OFF_TIME 255 HBMC_CH1_CFG_TEMP001_OFF_TIME 255 HBMC_CH1_CFG_TEMP010_OFF_TIME 127 HBMC_CH1_CFG_TEMP011_OFF_TIME 255 HBMC_CH1_CFG_TEMP100_OFF_TIME 255 HBMC_CH1_CFG_TEMP101_OFF_TIME 255 HBMC_CH1_CFG_TEMP110_OFF_TIME 127 HBMC_CH1_CFG_TEMP111_OFF_TIME 127 HBMC_CH1_CFG_RMW_EN disable HBMC_CH1_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH1_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH1_CFG_HBMCC2HPTRDLY 0 HBMC_CH1_HBM_TCCDL_BL4 4 HBMC_CH1_HBM_TRTW 15 HBMC_CH1_HBM_TFAW 16 HBMC_CH1_HBM_TEAW 24 HBMC_CH1_CFG_HBMC_PC0_FAW 5 HBMC_CH1_CFG_HBMC_PC0_RTI 1 HBMC_CH1_CFG_HBMC_PC0_RTW 13 HBMC_CH1_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH1_CFG_HBMC_PC1_FAW 5 HBMC_CH1_CFG_HBMC_PC1_RTI 2 HBMC_CH1_CFG_HBMC_PC1_RTW 13 HBMC_CH1_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH1_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH1_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH2_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH2_HBM_TRRDL 4 HBMC_CH2_HBM_TRCDRD 12 HBMC_CH2_HBM_TRCDWR 8 HBMC_CH2_HBM_TRTPL_BL4 5 HBMC_CH2_HBM_TRTPS_BL4 4 HBMC_CH2_HBM_TRP 12 HBMC_CH2_HBM_TCCDS_BL4 2 HBMC_CH2_HBM_TCCDR 3 HBMC_CH2_HBM_TWR 13 HBMC_CH2_HBM_TWTRL 7 HBMC_CH2_HBM_TWTRS 3 HBMC_CH2_HBM_TDQSS_MAX_PS 200 HBMC_CH2_HBM_TDQSS_MIN_PS 200 HBMC_CH2_HBM_TDQSCK_MAX_PS 3500 HBMC_CH2_HBM_TDQSQ_MAX_PS 105 HBMC_CH2_HBM_PARAM_TYPE hbm_param_min HBMC_CH2_RFSH_POLICY rfsh_policy_flexible HBMC_CH2_HBM_TREFI 3120 HBMC_CH2_HBM_TCKSRE 8 HBMC_CH2_HBM_TCKSRX 8 HBMC_CH2_HBM_TXS 216 HBMC_CH2_HBM_TCKESR 7 HBMC_CH2_HBM_TXP 6 HBMC_CH2_HBM_TPD 6 HBMC_CH2_CFG_HBMC_MODES prod HBMC_CH2_CORE_CLOCK_MHZ 350 HBMC_CH2_CORE_CLOCK_PS 1000 HBMC_CH2_CFG_CHANNEL_EN enable HBMC_CH2_CFG_TR_ORDER enable HBMC_CH2_CFG_ADDR_ORDER bgrbc HBMC_CH2_CFG_USER_RD_AP_POL rdap_hint HBMC_CH2_CFG_USER_WR_AP_POL wrap_hint HBMC_CH2_CFG_RID_DEPENDENCY_EN enable HBMC_CH2_CFG_HBMC_TX_BYPASS disable HBMC_CH2_CFG_HBMC_RX_BYPASS disable HBMC_CH2_CFG_P2HPEMUEN 0 HBMC_CH2_CFG_RMPTREN disable HBMC_CH2_CFG_RMPTRENDLY00 4 HBMC_CH2_CFG_RMPTRENDLY01 3 HBMC_CH2_CFG_RMPTRENDLY02 2 HBMC_CH2_CFG_RMPTRENDLY03 1 HBMC_CH2_CFG_RMPTRENDLY04 0 HBMC_CH2_HBM_TRAS 27 HBMC_CH2_HBM_TRRDS 4 HBMC_CH2_HBMC_OFFSET 1 HBMC_CH2_HBMC_RATE_VALUE rate_half HBMC_CH2_HBM_CLOCK_MHZ 800 HBMC_CH2_HBM_CLOCK_PS 1250 HBMC_CH2_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH2_HBM_TRFC 208 HBMC_CH2_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH2_EXT_RDIE 2 HBMC_CH2_TEMP000_THROTTLE_RATIO 0 HBMC_CH2_TEMP001_THROTTLE_RATIO 0 HBMC_CH2_TEMP010_THROTTLE_RATIO 50 HBMC_CH2_TEMP011_THROTTLE_RATIO 0 HBMC_CH2_TEMP100_THROTTLE_RATIO 0 HBMC_CH2_TEMP101_THROTTLE_RATIO 0 HBMC_CH2_TEMP110_THROTTLE_RATIO 50 HBMC_CH2_TEMP111_THROTTLE_RATIO 50 HBMC_CH2_CORE_CLK_MODE hr_asyn HBMC_CH2_CFG_HBMC_BL 4 HBMC_CH2_USER_STRB_EN enable HBMC_CH2_CFG_TBHMCRSTMIN 0 HBMC_CH2_CFG_RESET_COUNT 0 HBMC_CH2_CFG_HBMC_PC0_WL 6 HBMC_CH2_CFG_HBMC_PC0_RL 18 HBMC_CH2_CFG_HBMC_PC1_WL 6 HBMC_CH2_CFG_HBMC_PC1_RL 18 HBMC_CH2_CFG_POSTCAL_STATE sr HBMC_CH2_CFG_UFIC2PDLY 0 HBMC_CH2_CFG_UFIP2CDLY 0 HBMC_CH2_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH2_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH2_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH2_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH2_CFG_HBMC_PC0_SCR_EN enable HBMC_CH2_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH2_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH2_CFG_HBMC_PC1_SCR_EN enable HBMC_CH2_CFG_FLIP_MODE enable HBMC_CH2_CFG_DENSITY 1 HBMC_CH2_CFG_USER_DATA_WIDTH b256 HBMC_CH2_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH2_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH2_CFG_CB_RVALID_GATE_EN enable HBMC_CH2_CFG_CB_BVALID_GATE_EN enable HBMC_CH2_CFG_ADDRCHNLMUXEN disable HBMC_CH2_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH2_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH2_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH2_CFG_RCQ_AGE_LIMIT 32 HBMC_CH2_CFG_RDB_RSVD_ENTRY 0 HBMC_CH2_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH2_CFG_PC0_CMD2RDEN 15 HBMC_CH2_CFG_PC1_CMD2RDEN 16 HBMC_CH2_CFG_PC0_CMD2RDIE 13 HBMC_CH2_CFG_PC1_CMD2RDIE 14 HBMC_CH2_CFG_PC0_DATAOE_ON 2 HBMC_CH2_CFG_PC1_DATAOE_ON 2 HBMC_CH2_CFG_PC0_CMD2DATA 3 HBMC_CH2_CFG_PC1_CMD2DATA 4 HBMC_CH2_CFG_WDB_RSVD_ENTRY 32 HBMC_CH2_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH2_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH2_CFG_WCQ_LWM 8 HBMC_CH2_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH2_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH2_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH2_CFG_PC0_CMD2WDQS 2 HBMC_CH2_CFG_PC1_CMD2WDQS 3 HBMC_CH2_CFG_PC0_CMD2DATAOE 3 HBMC_CH2_CFG_PC1_CMD2DATAOE 4 HBMC_CH2_CFG_CB_MAJOR_MODE_EN enable HBMC_CH2_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH2_CFG_RFSH_ALL_EN enable HBMC_CH2_CFG_RFSH_PB_EN disable HBMC_CH2_CFG_USER_RFSH_PB_EN enable HBMC_CH2_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH2_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH2_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH2_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH2_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH2_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH2_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH2_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH2_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH2_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH2_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH2_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH2_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH2_CFG_TEMP_FILTER_EN enable HBMC_CH2_CFG_CATTRIP_FILTER_EN enable HBMC_CH2_CFG_CB_BYPASS_CATTRIP disable HBMC_CH2_CFG_CB_TEMP_SELECT disable HBMC_CH2_CFG_F2C_TEMP_UPDATE disable HBMC_CH2_CFG_F2C_TEMP 3 HBMC_CH2_CFG_ADDR_SCR none HBMC_CH2_CFG_ADDR_SPRD disable HBMC_CH2_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH2_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH2_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH2_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH2_CFG_CB_DEPENDENCY_MODE enable HBMC_CH2_CFG_MECC_EN disable HBMC_CH2_CFG_CA_PAR_EN enable HBMC_CH2_CFG_WR_PAR_EN enable HBMC_CH2_CFG_RD_PAR_EN enable HBMC_CH2_CFG_WR_DM_EN enable HBMC_CH2_CFG_RD_DM_EN disable HBMC_CH2_CFG_POWER_DOWN_EN enable HBMC_CH2_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH2_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH2_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH2_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH2_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH2_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH2_CFG_SELF_RFSH_EN enable HBMC_CH2_H0_FR_CLK_STCFG_EN disable HBMC_CH2_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH2_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH2_CFG_HBMC_CORECLK_PROG_DELAY1 4095 HBMC_CH2_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH2_CFG_HBMCPTRENSYNCSEL enable HBMC_CH2_CFG_UB48MODE enable HBMC_CH2_CFG_HBMCH2CPTRSTART 6 HBMC_CH2_CFG_DWORD_LPBKEN disable HBMC_CH2_CFG_AWORD_LPBEN disable HBMC_CH2_CFG_DWORD_LPBKSEL disable HBMC_CH2_CFG_AWORD_LPBKSEL 0 HBMC_CH2_CFG_OBSGRPSEL 0 HBMC_CH2_CFG_OBSSIGSEL 0 HBMC_CH2_CFG_MEM_MCE disable HBMC_CH2_CFG_MEM_WA 6 HBMC_CH2_CFG_MEM_RMCE 1 HBMC_CH2_CFG_MEM_WMCE 1 HBMC_CH2_CFG_MEM_WPULSE 2 HBMC_CH2_CFG_SRAM_ECC_ENABLE enable HBMC_CH2_CFG_PC0_SRAM_INJD disable HBMC_CH2_CFG_PC0_SRAM_INJS disable HBMC_CH2_CFG_PC1_SRAM_INJD disable HBMC_CH2_CFG_PC1_SRAM_INJS disable HBMC_CH2_CFG_SRAM_SERRINTEN enable HBMC_CH2_CFG_SRAM_SLVERR_DIS disable HBMC_CH2_MMR_USER_TRIGGER disable HBMC_CH2_MMR_USER_RDWR disable HBMC_CH2_MMR_USER_BYTEENABLE 0 HBMC_CH2_MMR_USER_ADDR 0 HBMC_CH2_MMR_USER_WRDATA 0 HBMC_CH2_MMR_SBOWN_REQ disable HBMC_CH2_MMR_SBOWN_DELAY 100 HBMC_CH2_CFG_SKETCH1 3 HBMC_CH2_CFG_SKETCH2 0 HBMC_CH2_CFG_TST_PATTERN 0 HBMC_CH2_CFG_TST_START_ADDR 0 HBMC_CH2_CFG_TST_BURST_LEN 0 HBMC_CH2_CFG_TST_GEN_CMD 0 HBMC_CH2_CFG_AXI_TRAFFIC_SEL disable HBMC_CH2_CFG_TST_PC_SEL disable HBMC_CH2_CFG_TST_TRIGGER disable HBMC_CH2_CFG_TST_TIME_OUT 0 HBMC_CH2_HBMC_RATE 2 HBMC_CH2_HBM_TRFCSB 128 HBMC_CH2_HBM_TRREFD 7 HBMC_CH2_UFI_TRDEN 23 HBMC_CH2_CFG_HBMC_PC0_WTP 10 HBMC_CH2_CFG_HBMC_PC1_WTP 10 HBMC_CH2_CFG_HBMC_PC0_ITP 19 HBMC_CH2_CFG_HBMC_PC1_ITP 19 HBMC_CH2_CFG_HBMC_PC0_RTP 2 HBMC_CH2_CFG_HBMC_PC1_RTP 2 HBMC_CH2_CFG_PAR_LAT 1 HBMC_CH2_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH2_CFG_HBMC_PC0_ATI 13 HBMC_CH2_CFG_HBMC_PC0_ITI 19 HBMC_CH2_CFG_HBMC_PC0_ATA 19 HBMC_CH2_CFG_HBMC_PC0_ITA 25 HBMC_CH2_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH2_CFG_HBMC_PC0_ATP 13 HBMC_CH2_CFG_HBMC_PC0_ATR 6 HBMC_CH2_CFG_HBMC_PC0_ITR 12 HBMC_CH2_CFG_HBMC_PC0_ATW 5 HBMC_CH2_CFG_HBMC_PC0_ITW 10 HBMC_CH2_CFG_HBMC_PC0_PTA 5 HBMC_CH2_CFG_HBMC_PC0_WTI 9 HBMC_CH2_CFG_HBMC_PC0_RTA 7 HBMC_CH2_CFG_HBMC_PC0_WTA 15 HBMC_CH2_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH2_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH2_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH2_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH2_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH2_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH2_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH2_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH2_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH2_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH2_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH2_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH2_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH2_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH2_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH2_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH2_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH2_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH2_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH2_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH2_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH2_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH2_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH2_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH2_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH2_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH2_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH2_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH2_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH2_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH2_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH2_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH2_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH2_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH2_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH2_CFG_HBMC_PC1_ATI 13 HBMC_CH2_CFG_HBMC_PC1_ITI 19 HBMC_CH2_CFG_HBMC_PC1_ATA 19 HBMC_CH2_CFG_HBMC_PC1_ITA 25 HBMC_CH2_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH2_CFG_HBMC_PC1_ATP 13 HBMC_CH2_CFG_HBMC_PC1_ATR 5 HBMC_CH2_CFG_HBMC_PC1_ITR 11 HBMC_CH2_CFG_HBMC_PC1_ATW 5 HBMC_CH2_CFG_HBMC_PC1_ITW 9 HBMC_CH2_CFG_HBMC_PC1_PTA 5 HBMC_CH2_CFG_HBMC_PC1_WTI 10 HBMC_CH2_CFG_HBMC_PC1_RTA 8 HBMC_CH2_CFG_HBMC_PC1_WTA 16 HBMC_CH2_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH2_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH2_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH2_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH2_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH2_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH2_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH2_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH2_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH2_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH2_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH2_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH2_CFG_PSEUDO_BL8_EN disable HBMC_CH2_CFG_CB_WREADY_GATE_EN disable HBMC_CH2_CFG_PC0_RDEN_ON 5 HBMC_CH2_CFG_PC1_RDEN_ON 5 HBMC_CH2_CFG_PC0_RDIE_ON 9 HBMC_CH2_CFG_PC1_RDIE_ON 9 HBMC_CH2_CFG_PC0_CMD2RD 30 HBMC_CH2_CFG_PC1_CMD2RD 31 HBMC_CH2_CFG_PC0_CMD2RDPAR 31 HBMC_CH2_CFG_PC1_CMD2RDPAR 32 HBMC_CH2_CFG_PC0_WDQS_ON 4 HBMC_CH2_CFG_PC1_WDQS_ON 4 HBMC_CH2_CFG_WCQ_HWM 24 HBMC_CH2_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH2_CFG_THROTTLE_EN enable HBMC_CH2_CFG_TEMP000_ON_TIME 0 HBMC_CH2_CFG_TEMP001_ON_TIME 0 HBMC_CH2_CFG_TEMP010_ON_TIME 127 HBMC_CH2_CFG_TEMP011_ON_TIME 0 HBMC_CH2_CFG_TEMP100_ON_TIME 0 HBMC_CH2_CFG_TEMP101_ON_TIME 0 HBMC_CH2_CFG_TEMP110_ON_TIME 127 HBMC_CH2_CFG_TEMP111_ON_TIME 127 HBMC_CH2_CFG_TEMP000_OFF_TIME 255 HBMC_CH2_CFG_TEMP001_OFF_TIME 255 HBMC_CH2_CFG_TEMP010_OFF_TIME 127 HBMC_CH2_CFG_TEMP011_OFF_TIME 255 HBMC_CH2_CFG_TEMP100_OFF_TIME 255 HBMC_CH2_CFG_TEMP101_OFF_TIME 255 HBMC_CH2_CFG_TEMP110_OFF_TIME 127 HBMC_CH2_CFG_TEMP111_OFF_TIME 127 HBMC_CH2_CFG_RMW_EN disable HBMC_CH2_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH2_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH2_CFG_HBMCC2HPTRDLY 0 HBMC_CH2_HBM_TCCDL_BL4 4 HBMC_CH2_HBM_TRTW 15 HBMC_CH2_HBM_TFAW 16 HBMC_CH2_HBM_TEAW 24 HBMC_CH2_CFG_HBMC_PC0_FAW 5 HBMC_CH2_CFG_HBMC_PC0_RTI 1 HBMC_CH2_CFG_HBMC_PC0_RTW 13 HBMC_CH2_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH2_CFG_HBMC_PC1_FAW 5 HBMC_CH2_CFG_HBMC_PC1_RTI 2 HBMC_CH2_CFG_HBMC_PC1_RTW 13 HBMC_CH2_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH2_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH2_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH3_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH3_HBM_TRRDL 4 HBMC_CH3_HBM_TRCDRD 12 HBMC_CH3_HBM_TRCDWR 8 HBMC_CH3_HBM_TRTPL_BL4 5 HBMC_CH3_HBM_TRTPS_BL4 4 HBMC_CH3_HBM_TRP 12 HBMC_CH3_HBM_TCCDS_BL4 2 HBMC_CH3_HBM_TCCDR 3 HBMC_CH3_HBM_TWR 13 HBMC_CH3_HBM_TWTRL 7 HBMC_CH3_HBM_TWTRS 3 HBMC_CH3_HBM_TDQSS_MAX_PS 200 HBMC_CH3_HBM_TDQSS_MIN_PS 200 HBMC_CH3_HBM_TDQSCK_MAX_PS 3500 HBMC_CH3_HBM_TDQSQ_MAX_PS 105 HBMC_CH3_HBM_PARAM_TYPE hbm_param_min HBMC_CH3_RFSH_POLICY rfsh_policy_flexible HBMC_CH3_HBM_TREFI 3120 HBMC_CH3_HBM_TCKSRE 8 HBMC_CH3_HBM_TCKSRX 8 HBMC_CH3_HBM_TXS 216 HBMC_CH3_HBM_TCKESR 7 HBMC_CH3_HBM_TXP 6 HBMC_CH3_HBM_TPD 6 HBMC_CH3_CFG_HBMC_MODES prod HBMC_CH3_CORE_CLOCK_MHZ 350 HBMC_CH3_CORE_CLOCK_PS 1000 HBMC_CH3_CFG_CHANNEL_EN enable HBMC_CH3_CFG_TR_ORDER enable HBMC_CH3_CFG_ADDR_ORDER bgrbc HBMC_CH3_CFG_USER_RD_AP_POL rdap_hint HBMC_CH3_CFG_USER_WR_AP_POL wrap_hint HBMC_CH3_CFG_RID_DEPENDENCY_EN enable HBMC_CH3_CFG_HBMC_TX_BYPASS disable HBMC_CH3_CFG_HBMC_RX_BYPASS disable HBMC_CH3_CFG_P2HPEMUEN 0 HBMC_CH3_CFG_RMPTREN disable HBMC_CH3_CFG_RMPTRENDLY00 4 HBMC_CH3_CFG_RMPTRENDLY01 3 HBMC_CH3_CFG_RMPTRENDLY02 2 HBMC_CH3_CFG_RMPTRENDLY03 1 HBMC_CH3_CFG_RMPTRENDLY04 0 HBMC_CH3_HBM_TRAS 27 HBMC_CH3_HBM_TRRDS 4 HBMC_CH3_HBMC_OFFSET 1 HBMC_CH3_HBMC_RATE_VALUE rate_half HBMC_CH3_HBM_CLOCK_MHZ 800 HBMC_CH3_HBM_CLOCK_PS 1250 HBMC_CH3_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH3_HBM_TRFC 208 HBMC_CH3_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH3_EXT_RDIE 2 HBMC_CH3_TEMP000_THROTTLE_RATIO 0 HBMC_CH3_TEMP001_THROTTLE_RATIO 0 HBMC_CH3_TEMP010_THROTTLE_RATIO 50 HBMC_CH3_TEMP011_THROTTLE_RATIO 0 HBMC_CH3_TEMP100_THROTTLE_RATIO 0 HBMC_CH3_TEMP101_THROTTLE_RATIO 0 HBMC_CH3_TEMP110_THROTTLE_RATIO 50 HBMC_CH3_TEMP111_THROTTLE_RATIO 50 HBMC_CH3_CORE_CLK_MODE hr_asyn HBMC_CH3_CFG_HBMC_BL 4 HBMC_CH3_USER_STRB_EN enable HBMC_CH3_CFG_TBHMCRSTMIN 0 HBMC_CH3_CFG_RESET_COUNT 0 HBMC_CH3_CFG_HBMC_PC0_WL 6 HBMC_CH3_CFG_HBMC_PC0_RL 18 HBMC_CH3_CFG_HBMC_PC1_WL 6 HBMC_CH3_CFG_HBMC_PC1_RL 18 HBMC_CH3_CFG_POSTCAL_STATE sr HBMC_CH3_CFG_UFIC2PDLY 0 HBMC_CH3_CFG_UFIP2CDLY 0 HBMC_CH3_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH3_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH3_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH3_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH3_CFG_HBMC_PC0_SCR_EN enable HBMC_CH3_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH3_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH3_CFG_HBMC_PC1_SCR_EN enable HBMC_CH3_CFG_FLIP_MODE enable HBMC_CH3_CFG_DENSITY 1 HBMC_CH3_CFG_USER_DATA_WIDTH b256 HBMC_CH3_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH3_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH3_CFG_CB_RVALID_GATE_EN enable HBMC_CH3_CFG_CB_BVALID_GATE_EN enable HBMC_CH3_CFG_ADDRCHNLMUXEN disable HBMC_CH3_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH3_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH3_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH3_CFG_RCQ_AGE_LIMIT 32 HBMC_CH3_CFG_RDB_RSVD_ENTRY 0 HBMC_CH3_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH3_CFG_PC0_CMD2RDEN 15 HBMC_CH3_CFG_PC1_CMD2RDEN 16 HBMC_CH3_CFG_PC0_CMD2RDIE 13 HBMC_CH3_CFG_PC1_CMD2RDIE 14 HBMC_CH3_CFG_PC0_DATAOE_ON 2 HBMC_CH3_CFG_PC1_DATAOE_ON 2 HBMC_CH3_CFG_PC0_CMD2DATA 3 HBMC_CH3_CFG_PC1_CMD2DATA 4 HBMC_CH3_CFG_WDB_RSVD_ENTRY 32 HBMC_CH3_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH3_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH3_CFG_WCQ_LWM 8 HBMC_CH3_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH3_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH3_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH3_CFG_PC0_CMD2WDQS 2 HBMC_CH3_CFG_PC1_CMD2WDQS 3 HBMC_CH3_CFG_PC0_CMD2DATAOE 3 HBMC_CH3_CFG_PC1_CMD2DATAOE 4 HBMC_CH3_CFG_CB_MAJOR_MODE_EN enable HBMC_CH3_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH3_CFG_RFSH_ALL_EN enable HBMC_CH3_CFG_RFSH_PB_EN disable HBMC_CH3_CFG_USER_RFSH_PB_EN enable HBMC_CH3_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH3_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH3_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH3_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH3_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH3_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH3_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH3_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH3_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH3_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH3_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH3_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH3_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH3_CFG_TEMP_FILTER_EN enable HBMC_CH3_CFG_CATTRIP_FILTER_EN enable HBMC_CH3_CFG_CB_BYPASS_CATTRIP disable HBMC_CH3_CFG_CB_TEMP_SELECT disable HBMC_CH3_CFG_F2C_TEMP_UPDATE disable HBMC_CH3_CFG_F2C_TEMP 3 HBMC_CH3_CFG_ADDR_SCR none HBMC_CH3_CFG_ADDR_SPRD disable HBMC_CH3_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH3_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH3_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH3_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH3_CFG_CB_DEPENDENCY_MODE enable HBMC_CH3_CFG_MECC_EN disable HBMC_CH3_CFG_CA_PAR_EN enable HBMC_CH3_CFG_WR_PAR_EN enable HBMC_CH3_CFG_RD_PAR_EN enable HBMC_CH3_CFG_WR_DM_EN enable HBMC_CH3_CFG_RD_DM_EN disable HBMC_CH3_CFG_POWER_DOWN_EN enable HBMC_CH3_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH3_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH3_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH3_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH3_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH3_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH3_CFG_SELF_RFSH_EN enable HBMC_CH3_H0_FR_CLK_STCFG_EN disable HBMC_CH3_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH3_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH3_CFG_HBMC_CORECLK_PROG_DELAY1 4095 HBMC_CH3_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH3_CFG_HBMCPTRENSYNCSEL enable HBMC_CH3_CFG_UB48MODE enable HBMC_CH3_CFG_HBMCH2CPTRSTART 6 HBMC_CH3_CFG_DWORD_LPBKEN disable HBMC_CH3_CFG_AWORD_LPBEN disable HBMC_CH3_CFG_DWORD_LPBKSEL disable HBMC_CH3_CFG_AWORD_LPBKSEL 0 HBMC_CH3_CFG_OBSGRPSEL 0 HBMC_CH3_CFG_OBSSIGSEL 0 HBMC_CH3_CFG_MEM_MCE disable HBMC_CH3_CFG_MEM_WA 6 HBMC_CH3_CFG_MEM_RMCE 1 HBMC_CH3_CFG_MEM_WMCE 1 HBMC_CH3_CFG_MEM_WPULSE 2 HBMC_CH3_CFG_SRAM_ECC_ENABLE enable HBMC_CH3_CFG_PC0_SRAM_INJD disable HBMC_CH3_CFG_PC0_SRAM_INJS disable HBMC_CH3_CFG_PC1_SRAM_INJD disable HBMC_CH3_CFG_PC1_SRAM_INJS disable HBMC_CH3_CFG_SRAM_SERRINTEN enable HBMC_CH3_CFG_SRAM_SLVERR_DIS disable HBMC_CH3_MMR_USER_TRIGGER disable HBMC_CH3_MMR_USER_RDWR disable HBMC_CH3_MMR_USER_BYTEENABLE 0 HBMC_CH3_MMR_USER_ADDR 0 HBMC_CH3_MMR_USER_WRDATA 0 HBMC_CH3_MMR_SBOWN_REQ disable HBMC_CH3_MMR_SBOWN_DELAY 100 HBMC_CH3_CFG_SKETCH1 3 HBMC_CH3_CFG_SKETCH2 0 HBMC_CH3_CFG_TST_PATTERN 0 HBMC_CH3_CFG_TST_START_ADDR 0 HBMC_CH3_CFG_TST_BURST_LEN 0 HBMC_CH3_CFG_TST_GEN_CMD 0 HBMC_CH3_CFG_AXI_TRAFFIC_SEL disable HBMC_CH3_CFG_TST_PC_SEL disable HBMC_CH3_CFG_TST_TRIGGER disable HBMC_CH3_CFG_TST_TIME_OUT 0 HBMC_CH3_HBMC_RATE 2 HBMC_CH3_HBM_TRFCSB 128 HBMC_CH3_HBM_TRREFD 7 HBMC_CH3_UFI_TRDEN 23 HBMC_CH3_CFG_HBMC_PC0_WTP 10 HBMC_CH3_CFG_HBMC_PC1_WTP 10 HBMC_CH3_CFG_HBMC_PC0_ITP 19 HBMC_CH3_CFG_HBMC_PC1_ITP 19 HBMC_CH3_CFG_HBMC_PC0_RTP 2 HBMC_CH3_CFG_HBMC_PC1_RTP 2 HBMC_CH3_CFG_PAR_LAT 1 HBMC_CH3_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH3_CFG_HBMC_PC0_ATI 13 HBMC_CH3_CFG_HBMC_PC0_ITI 19 HBMC_CH3_CFG_HBMC_PC0_ATA 19 HBMC_CH3_CFG_HBMC_PC0_ITA 25 HBMC_CH3_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH3_CFG_HBMC_PC0_ATP 13 HBMC_CH3_CFG_HBMC_PC0_ATR 6 HBMC_CH3_CFG_HBMC_PC0_ITR 12 HBMC_CH3_CFG_HBMC_PC0_ATW 5 HBMC_CH3_CFG_HBMC_PC0_ITW 10 HBMC_CH3_CFG_HBMC_PC0_PTA 5 HBMC_CH3_CFG_HBMC_PC0_WTI 9 HBMC_CH3_CFG_HBMC_PC0_RTA 7 HBMC_CH3_CFG_HBMC_PC0_WTA 15 HBMC_CH3_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH3_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH3_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH3_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH3_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH3_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH3_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH3_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH3_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH3_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH3_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH3_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH3_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH3_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH3_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH3_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH3_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH3_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH3_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH3_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH3_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH3_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH3_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH3_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH3_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH3_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH3_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH3_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH3_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH3_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH3_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH3_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH3_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH3_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH3_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH3_CFG_HBMC_PC1_ATI 13 HBMC_CH3_CFG_HBMC_PC1_ITI 19 HBMC_CH3_CFG_HBMC_PC1_ATA 19 HBMC_CH3_CFG_HBMC_PC1_ITA 25 HBMC_CH3_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH3_CFG_HBMC_PC1_ATP 13 HBMC_CH3_CFG_HBMC_PC1_ATR 5 HBMC_CH3_CFG_HBMC_PC1_ITR 11 HBMC_CH3_CFG_HBMC_PC1_ATW 5 HBMC_CH3_CFG_HBMC_PC1_ITW 9 HBMC_CH3_CFG_HBMC_PC1_PTA 5 HBMC_CH3_CFG_HBMC_PC1_WTI 10 HBMC_CH3_CFG_HBMC_PC1_RTA 8 HBMC_CH3_CFG_HBMC_PC1_WTA 16 HBMC_CH3_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH3_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH3_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH3_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH3_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH3_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH3_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH3_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH3_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH3_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH3_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH3_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH3_CFG_PSEUDO_BL8_EN disable HBMC_CH3_CFG_CB_WREADY_GATE_EN disable HBMC_CH3_CFG_PC0_RDEN_ON 5 HBMC_CH3_CFG_PC1_RDEN_ON 5 HBMC_CH3_CFG_PC0_RDIE_ON 9 HBMC_CH3_CFG_PC1_RDIE_ON 9 HBMC_CH3_CFG_PC0_CMD2RD 30 HBMC_CH3_CFG_PC1_CMD2RD 31 HBMC_CH3_CFG_PC0_CMD2RDPAR 31 HBMC_CH3_CFG_PC1_CMD2RDPAR 32 HBMC_CH3_CFG_PC0_WDQS_ON 4 HBMC_CH3_CFG_PC1_WDQS_ON 4 HBMC_CH3_CFG_WCQ_HWM 24 HBMC_CH3_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH3_CFG_THROTTLE_EN enable HBMC_CH3_CFG_TEMP000_ON_TIME 0 HBMC_CH3_CFG_TEMP001_ON_TIME 0 HBMC_CH3_CFG_TEMP010_ON_TIME 127 HBMC_CH3_CFG_TEMP011_ON_TIME 0 HBMC_CH3_CFG_TEMP100_ON_TIME 0 HBMC_CH3_CFG_TEMP101_ON_TIME 0 HBMC_CH3_CFG_TEMP110_ON_TIME 127 HBMC_CH3_CFG_TEMP111_ON_TIME 127 HBMC_CH3_CFG_TEMP000_OFF_TIME 255 HBMC_CH3_CFG_TEMP001_OFF_TIME 255 HBMC_CH3_CFG_TEMP010_OFF_TIME 127 HBMC_CH3_CFG_TEMP011_OFF_TIME 255 HBMC_CH3_CFG_TEMP100_OFF_TIME 255 HBMC_CH3_CFG_TEMP101_OFF_TIME 255 HBMC_CH3_CFG_TEMP110_OFF_TIME 127 HBMC_CH3_CFG_TEMP111_OFF_TIME 127 HBMC_CH3_CFG_RMW_EN disable HBMC_CH3_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH3_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH3_CFG_HBMCC2HPTRDLY 0 HBMC_CH3_HBM_TCCDL_BL4 4 HBMC_CH3_HBM_TRTW 15 HBMC_CH3_HBM_TFAW 16 HBMC_CH3_HBM_TEAW 24 HBMC_CH3_CFG_HBMC_PC0_FAW 5 HBMC_CH3_CFG_HBMC_PC0_RTI 1 HBMC_CH3_CFG_HBMC_PC0_RTW 13 HBMC_CH3_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH3_CFG_HBMC_PC1_FAW 5 HBMC_CH3_CFG_HBMC_PC1_RTI 2 HBMC_CH3_CFG_HBMC_PC1_RTW 13 HBMC_CH3_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH3_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH3_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH4_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH4_HBM_TRRDL 4 HBMC_CH4_HBM_TRCDRD 12 HBMC_CH4_HBM_TRCDWR 8 HBMC_CH4_HBM_TRTPL_BL4 5 HBMC_CH4_HBM_TRTPS_BL4 4 HBMC_CH4_HBM_TRP 12 HBMC_CH4_HBM_TCCDS_BL4 2 HBMC_CH4_HBM_TCCDR 3 HBMC_CH4_HBM_TWR 13 HBMC_CH4_HBM_TWTRL 7 HBMC_CH4_HBM_TWTRS 3 HBMC_CH4_HBM_TDQSS_MAX_PS 200 HBMC_CH4_HBM_TDQSS_MIN_PS 200 HBMC_CH4_HBM_TDQSCK_MAX_PS 3500 HBMC_CH4_HBM_TDQSQ_MAX_PS 105 HBMC_CH4_HBM_PARAM_TYPE hbm_param_min HBMC_CH4_RFSH_POLICY rfsh_policy_flexible HBMC_CH4_HBM_TREFI 3120 HBMC_CH4_HBM_TCKSRE 8 HBMC_CH4_HBM_TCKSRX 8 HBMC_CH4_HBM_TXS 216 HBMC_CH4_HBM_TCKESR 7 HBMC_CH4_HBM_TXP 6 HBMC_CH4_HBM_TPD 6 HBMC_CH4_CFG_HBMC_MODES prod HBMC_CH4_CORE_CLOCK_MHZ 350 HBMC_CH4_CORE_CLOCK_PS 1000 HBMC_CH4_CFG_CHANNEL_EN enable HBMC_CH4_CFG_TR_ORDER enable HBMC_CH4_CFG_ADDR_ORDER bgrbc HBMC_CH4_CFG_USER_RD_AP_POL rdap_hint HBMC_CH4_CFG_USER_WR_AP_POL wrap_hint HBMC_CH4_CFG_RID_DEPENDENCY_EN enable HBMC_CH4_CFG_HBMC_TX_BYPASS disable HBMC_CH4_CFG_HBMC_RX_BYPASS disable HBMC_CH4_CFG_P2HPEMUEN 2 HBMC_CH4_CFG_RMPTREN disable HBMC_CH4_CFG_RMPTRENDLY00 6 HBMC_CH4_CFG_RMPTRENDLY01 7 HBMC_CH4_CFG_RMPTRENDLY02 8 HBMC_CH4_CFG_RMPTRENDLY03 9 HBMC_CH4_CFG_RMPTRENDLY04 10 HBMC_CH4_HBM_TRAS 27 HBMC_CH4_HBM_TRRDS 4 HBMC_CH4_HBMC_OFFSET 1 HBMC_CH4_HBMC_RATE_VALUE rate_half HBMC_CH4_HBM_CLOCK_MHZ 800 HBMC_CH4_HBM_CLOCK_PS 1250 HBMC_CH4_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH4_HBM_TRFC 208 HBMC_CH4_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH4_EXT_RDIE 2 HBMC_CH4_TEMP000_THROTTLE_RATIO 0 HBMC_CH4_TEMP001_THROTTLE_RATIO 0 HBMC_CH4_TEMP010_THROTTLE_RATIO 50 HBMC_CH4_TEMP011_THROTTLE_RATIO 0 HBMC_CH4_TEMP100_THROTTLE_RATIO 0 HBMC_CH4_TEMP101_THROTTLE_RATIO 0 HBMC_CH4_TEMP110_THROTTLE_RATIO 50 HBMC_CH4_TEMP111_THROTTLE_RATIO 50 HBMC_CH4_CORE_CLK_MODE hr_asyn HBMC_CH4_CFG_HBMC_BL 4 HBMC_CH4_USER_STRB_EN enable HBMC_CH4_CFG_TBHMCRSTMIN 0 HBMC_CH4_CFG_RESET_COUNT 0 HBMC_CH4_CFG_HBMC_PC0_WL 6 HBMC_CH4_CFG_HBMC_PC0_RL 18 HBMC_CH4_CFG_HBMC_PC1_WL 6 HBMC_CH4_CFG_HBMC_PC1_RL 18 HBMC_CH4_CFG_POSTCAL_STATE sr HBMC_CH4_CFG_UFIC2PDLY 0 HBMC_CH4_CFG_UFIP2CDLY 0 HBMC_CH4_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH4_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH4_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH4_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH4_CFG_HBMC_PC0_SCR_EN enable HBMC_CH4_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH4_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH4_CFG_HBMC_PC1_SCR_EN enable HBMC_CH4_CFG_FLIP_MODE enable HBMC_CH4_CFG_DENSITY 1 HBMC_CH4_CFG_USER_DATA_WIDTH b256 HBMC_CH4_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH4_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH4_CFG_CB_RVALID_GATE_EN enable HBMC_CH4_CFG_CB_BVALID_GATE_EN enable HBMC_CH4_CFG_ADDRCHNLMUXEN disable HBMC_CH4_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH4_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH4_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH4_CFG_RCQ_AGE_LIMIT 32 HBMC_CH4_CFG_RDB_RSVD_ENTRY 0 HBMC_CH4_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH4_CFG_PC0_CMD2RDEN 15 HBMC_CH4_CFG_PC1_CMD2RDEN 16 HBMC_CH4_CFG_PC0_CMD2RDIE 13 HBMC_CH4_CFG_PC1_CMD2RDIE 14 HBMC_CH4_CFG_PC0_DATAOE_ON 2 HBMC_CH4_CFG_PC1_DATAOE_ON 2 HBMC_CH4_CFG_PC0_CMD2DATA 3 HBMC_CH4_CFG_PC1_CMD2DATA 4 HBMC_CH4_CFG_WDB_RSVD_ENTRY 32 HBMC_CH4_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH4_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH4_CFG_WCQ_LWM 8 HBMC_CH4_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH4_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH4_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH4_CFG_PC0_CMD2WDQS 2 HBMC_CH4_CFG_PC1_CMD2WDQS 3 HBMC_CH4_CFG_PC0_CMD2DATAOE 3 HBMC_CH4_CFG_PC1_CMD2DATAOE 4 HBMC_CH4_CFG_CB_MAJOR_MODE_EN enable HBMC_CH4_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH4_CFG_RFSH_ALL_EN enable HBMC_CH4_CFG_RFSH_PB_EN disable HBMC_CH4_CFG_USER_RFSH_PB_EN enable HBMC_CH4_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH4_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH4_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH4_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH4_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH4_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH4_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH4_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH4_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH4_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH4_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH4_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH4_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH4_CFG_TEMP_FILTER_EN enable HBMC_CH4_CFG_CATTRIP_FILTER_EN enable HBMC_CH4_CFG_CB_BYPASS_CATTRIP disable HBMC_CH4_CFG_CB_TEMP_SELECT disable HBMC_CH4_CFG_F2C_TEMP_UPDATE disable HBMC_CH4_CFG_F2C_TEMP 3 HBMC_CH4_CFG_ADDR_SCR none HBMC_CH4_CFG_ADDR_SPRD disable HBMC_CH4_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH4_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH4_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH4_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH4_CFG_CB_DEPENDENCY_MODE enable HBMC_CH4_CFG_MECC_EN disable HBMC_CH4_CFG_CA_PAR_EN enable HBMC_CH4_CFG_WR_PAR_EN enable HBMC_CH4_CFG_RD_PAR_EN enable HBMC_CH4_CFG_WR_DM_EN enable HBMC_CH4_CFG_RD_DM_EN disable HBMC_CH4_CFG_POWER_DOWN_EN enable HBMC_CH4_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH4_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH4_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH4_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH4_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH4_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH4_CFG_SELF_RFSH_EN enable HBMC_CH4_H0_FR_CLK_STCFG_EN disable HBMC_CH4_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH4_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH4_CFG_HBMC_CORECLK_PROG_DELAY1 255 HBMC_CH4_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH4_CFG_HBMCPTRENSYNCSEL enable HBMC_CH4_CFG_UB48MODE enable HBMC_CH4_CFG_HBMCH2CPTRSTART 6 HBMC_CH4_CFG_DWORD_LPBKEN disable HBMC_CH4_CFG_AWORD_LPBEN disable HBMC_CH4_CFG_DWORD_LPBKSEL disable HBMC_CH4_CFG_AWORD_LPBKSEL 0 HBMC_CH4_CFG_OBSGRPSEL 0 HBMC_CH4_CFG_OBSSIGSEL 0 HBMC_CH4_CFG_MEM_MCE disable HBMC_CH4_CFG_MEM_WA 6 HBMC_CH4_CFG_MEM_RMCE 1 HBMC_CH4_CFG_MEM_WMCE 1 HBMC_CH4_CFG_MEM_WPULSE 2 HBMC_CH4_CFG_SRAM_ECC_ENABLE enable HBMC_CH4_CFG_PC0_SRAM_INJD disable HBMC_CH4_CFG_PC0_SRAM_INJS disable HBMC_CH4_CFG_PC1_SRAM_INJD disable HBMC_CH4_CFG_PC1_SRAM_INJS disable HBMC_CH4_CFG_SRAM_SERRINTEN enable HBMC_CH4_CFG_SRAM_SLVERR_DIS disable HBMC_CH4_MMR_USER_TRIGGER disable HBMC_CH4_MMR_USER_RDWR disable HBMC_CH4_MMR_USER_BYTEENABLE 0 HBMC_CH4_MMR_USER_ADDR 0 HBMC_CH4_MMR_USER_WRDATA 0 HBMC_CH4_MMR_SBOWN_REQ disable HBMC_CH4_MMR_SBOWN_DELAY 100 HBMC_CH4_CFG_SKETCH1 3 HBMC_CH4_CFG_SKETCH2 0 HBMC_CH4_CFG_TST_PATTERN 0 HBMC_CH4_CFG_TST_START_ADDR 0 HBMC_CH4_CFG_TST_BURST_LEN 0 HBMC_CH4_CFG_TST_GEN_CMD 0 HBMC_CH4_CFG_AXI_TRAFFIC_SEL disable HBMC_CH4_CFG_TST_PC_SEL disable HBMC_CH4_CFG_TST_TRIGGER disable HBMC_CH4_CFG_TST_TIME_OUT 0 HBMC_CH4_HBMC_RATE 2 HBMC_CH4_HBM_TRFCSB 128 HBMC_CH4_HBM_TRREFD 7 HBMC_CH4_UFI_TRDEN 23 HBMC_CH4_CFG_HBMC_PC0_WTP 10 HBMC_CH4_CFG_HBMC_PC1_WTP 10 HBMC_CH4_CFG_HBMC_PC0_ITP 19 HBMC_CH4_CFG_HBMC_PC1_ITP 19 HBMC_CH4_CFG_HBMC_PC0_RTP 2 HBMC_CH4_CFG_HBMC_PC1_RTP 2 HBMC_CH4_CFG_PAR_LAT 1 HBMC_CH4_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH4_CFG_HBMC_PC0_ATI 13 HBMC_CH4_CFG_HBMC_PC0_ITI 19 HBMC_CH4_CFG_HBMC_PC0_ATA 19 HBMC_CH4_CFG_HBMC_PC0_ITA 25 HBMC_CH4_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH4_CFG_HBMC_PC0_ATP 13 HBMC_CH4_CFG_HBMC_PC0_ATR 6 HBMC_CH4_CFG_HBMC_PC0_ITR 12 HBMC_CH4_CFG_HBMC_PC0_ATW 5 HBMC_CH4_CFG_HBMC_PC0_ITW 10 HBMC_CH4_CFG_HBMC_PC0_PTA 5 HBMC_CH4_CFG_HBMC_PC0_WTI 9 HBMC_CH4_CFG_HBMC_PC0_RTA 7 HBMC_CH4_CFG_HBMC_PC0_WTA 15 HBMC_CH4_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH4_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH4_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH4_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH4_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH4_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH4_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH4_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH4_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH4_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH4_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH4_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH4_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH4_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH4_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH4_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH4_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH4_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH4_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH4_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH4_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH4_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH4_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH4_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH4_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH4_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH4_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH4_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH4_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH4_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH4_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH4_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH4_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH4_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH4_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH4_CFG_HBMC_PC1_ATI 13 HBMC_CH4_CFG_HBMC_PC1_ITI 19 HBMC_CH4_CFG_HBMC_PC1_ATA 19 HBMC_CH4_CFG_HBMC_PC1_ITA 25 HBMC_CH4_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH4_CFG_HBMC_PC1_ATP 13 HBMC_CH4_CFG_HBMC_PC1_ATR 5 HBMC_CH4_CFG_HBMC_PC1_ITR 11 HBMC_CH4_CFG_HBMC_PC1_ATW 5 HBMC_CH4_CFG_HBMC_PC1_ITW 9 HBMC_CH4_CFG_HBMC_PC1_PTA 5 HBMC_CH4_CFG_HBMC_PC1_WTI 10 HBMC_CH4_CFG_HBMC_PC1_RTA 8 HBMC_CH4_CFG_HBMC_PC1_WTA 16 HBMC_CH4_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH4_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH4_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH4_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH4_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH4_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH4_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH4_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH4_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH4_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH4_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH4_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH4_CFG_PSEUDO_BL8_EN disable HBMC_CH4_CFG_CB_WREADY_GATE_EN disable HBMC_CH4_CFG_PC0_RDEN_ON 5 HBMC_CH4_CFG_PC1_RDEN_ON 5 HBMC_CH4_CFG_PC0_RDIE_ON 9 HBMC_CH4_CFG_PC1_RDIE_ON 9 HBMC_CH4_CFG_PC0_CMD2RD 30 HBMC_CH4_CFG_PC1_CMD2RD 31 HBMC_CH4_CFG_PC0_CMD2RDPAR 31 HBMC_CH4_CFG_PC1_CMD2RDPAR 32 HBMC_CH4_CFG_PC0_WDQS_ON 4 HBMC_CH4_CFG_PC1_WDQS_ON 4 HBMC_CH4_CFG_WCQ_HWM 24 HBMC_CH4_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH4_CFG_THROTTLE_EN enable HBMC_CH4_CFG_TEMP000_ON_TIME 0 HBMC_CH4_CFG_TEMP001_ON_TIME 0 HBMC_CH4_CFG_TEMP010_ON_TIME 127 HBMC_CH4_CFG_TEMP011_ON_TIME 0 HBMC_CH4_CFG_TEMP100_ON_TIME 0 HBMC_CH4_CFG_TEMP101_ON_TIME 0 HBMC_CH4_CFG_TEMP110_ON_TIME 127 HBMC_CH4_CFG_TEMP111_ON_TIME 127 HBMC_CH4_CFG_TEMP000_OFF_TIME 255 HBMC_CH4_CFG_TEMP001_OFF_TIME 255 HBMC_CH4_CFG_TEMP010_OFF_TIME 127 HBMC_CH4_CFG_TEMP011_OFF_TIME 255 HBMC_CH4_CFG_TEMP100_OFF_TIME 255 HBMC_CH4_CFG_TEMP101_OFF_TIME 255 HBMC_CH4_CFG_TEMP110_OFF_TIME 127 HBMC_CH4_CFG_TEMP111_OFF_TIME 127 HBMC_CH4_CFG_RMW_EN disable HBMC_CH4_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH4_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH4_CFG_HBMCC2HPTRDLY 0 HBMC_CH4_HBM_TCCDL_BL4 4 HBMC_CH4_HBM_TRTW 15 HBMC_CH4_HBM_TFAW 16 HBMC_CH4_HBM_TEAW 24 HBMC_CH4_CFG_HBMC_PC0_FAW 5 HBMC_CH4_CFG_HBMC_PC0_RTI 1 HBMC_CH4_CFG_HBMC_PC0_RTW 13 HBMC_CH4_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH4_CFG_HBMC_PC1_FAW 5 HBMC_CH4_CFG_HBMC_PC1_RTI 2 HBMC_CH4_CFG_HBMC_PC1_RTW 13 HBMC_CH4_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH4_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH4_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH5_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH5_HBM_TRRDL 4 HBMC_CH5_HBM_TRCDRD 12 HBMC_CH5_HBM_TRCDWR 8 HBMC_CH5_HBM_TRTPL_BL4 5 HBMC_CH5_HBM_TRTPS_BL4 4 HBMC_CH5_HBM_TRP 12 HBMC_CH5_HBM_TCCDS_BL4 2 HBMC_CH5_HBM_TCCDR 3 HBMC_CH5_HBM_TWR 13 HBMC_CH5_HBM_TWTRL 7 HBMC_CH5_HBM_TWTRS 3 HBMC_CH5_HBM_TDQSS_MAX_PS 200 HBMC_CH5_HBM_TDQSS_MIN_PS 200 HBMC_CH5_HBM_TDQSCK_MAX_PS 3500 HBMC_CH5_HBM_TDQSQ_MAX_PS 105 HBMC_CH5_HBM_PARAM_TYPE hbm_param_min HBMC_CH5_RFSH_POLICY rfsh_policy_flexible HBMC_CH5_HBM_TREFI 3120 HBMC_CH5_HBM_TCKSRE 8 HBMC_CH5_HBM_TCKSRX 8 HBMC_CH5_HBM_TXS 216 HBMC_CH5_HBM_TCKESR 7 HBMC_CH5_HBM_TXP 6 HBMC_CH5_HBM_TPD 6 HBMC_CH5_CFG_HBMC_MODES prod HBMC_CH5_CORE_CLOCK_MHZ 350 HBMC_CH5_CORE_CLOCK_PS 1000 HBMC_CH5_CFG_CHANNEL_EN enable HBMC_CH5_CFG_TR_ORDER enable HBMC_CH5_CFG_ADDR_ORDER bgrbc HBMC_CH5_CFG_USER_RD_AP_POL rdap_hint HBMC_CH5_CFG_USER_WR_AP_POL wrap_hint HBMC_CH5_CFG_RID_DEPENDENCY_EN enable HBMC_CH5_CFG_HBMC_TX_BYPASS disable HBMC_CH5_CFG_HBMC_RX_BYPASS disable HBMC_CH5_CFG_P2HPEMUEN 2 HBMC_CH5_CFG_RMPTREN disable HBMC_CH5_CFG_RMPTRENDLY00 6 HBMC_CH5_CFG_RMPTRENDLY01 7 HBMC_CH5_CFG_RMPTRENDLY02 8 HBMC_CH5_CFG_RMPTRENDLY03 9 HBMC_CH5_CFG_RMPTRENDLY04 10 HBMC_CH5_HBM_TRAS 27 HBMC_CH5_HBM_TRRDS 4 HBMC_CH5_HBMC_OFFSET 1 HBMC_CH5_HBMC_RATE_VALUE rate_half HBMC_CH5_HBM_CLOCK_MHZ 800 HBMC_CH5_HBM_CLOCK_PS 1250 HBMC_CH5_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH5_HBM_TRFC 208 HBMC_CH5_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH5_EXT_RDIE 2 HBMC_CH5_TEMP000_THROTTLE_RATIO 0 HBMC_CH5_TEMP001_THROTTLE_RATIO 0 HBMC_CH5_TEMP010_THROTTLE_RATIO 50 HBMC_CH5_TEMP011_THROTTLE_RATIO 0 HBMC_CH5_TEMP100_THROTTLE_RATIO 0 HBMC_CH5_TEMP101_THROTTLE_RATIO 0 HBMC_CH5_TEMP110_THROTTLE_RATIO 50 HBMC_CH5_TEMP111_THROTTLE_RATIO 50 HBMC_CH5_CORE_CLK_MODE hr_asyn HBMC_CH5_CFG_HBMC_BL 4 HBMC_CH5_USER_STRB_EN enable HBMC_CH5_CFG_TBHMCRSTMIN 0 HBMC_CH5_CFG_RESET_COUNT 0 HBMC_CH5_CFG_HBMC_PC0_WL 6 HBMC_CH5_CFG_HBMC_PC0_RL 18 HBMC_CH5_CFG_HBMC_PC1_WL 6 HBMC_CH5_CFG_HBMC_PC1_RL 18 HBMC_CH5_CFG_POSTCAL_STATE sr HBMC_CH5_CFG_UFIC2PDLY 0 HBMC_CH5_CFG_UFIP2CDLY 0 HBMC_CH5_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH5_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH5_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH5_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH5_CFG_HBMC_PC0_SCR_EN enable HBMC_CH5_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH5_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH5_CFG_HBMC_PC1_SCR_EN enable HBMC_CH5_CFG_FLIP_MODE enable HBMC_CH5_CFG_DENSITY 1 HBMC_CH5_CFG_USER_DATA_WIDTH b256 HBMC_CH5_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH5_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH5_CFG_CB_RVALID_GATE_EN enable HBMC_CH5_CFG_CB_BVALID_GATE_EN enable HBMC_CH5_CFG_ADDRCHNLMUXEN disable HBMC_CH5_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH5_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH5_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH5_CFG_RCQ_AGE_LIMIT 32 HBMC_CH5_CFG_RDB_RSVD_ENTRY 0 HBMC_CH5_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH5_CFG_PC0_CMD2RDEN 15 HBMC_CH5_CFG_PC1_CMD2RDEN 16 HBMC_CH5_CFG_PC0_CMD2RDIE 13 HBMC_CH5_CFG_PC1_CMD2RDIE 14 HBMC_CH5_CFG_PC0_DATAOE_ON 2 HBMC_CH5_CFG_PC1_DATAOE_ON 2 HBMC_CH5_CFG_PC0_CMD2DATA 3 HBMC_CH5_CFG_PC1_CMD2DATA 4 HBMC_CH5_CFG_WDB_RSVD_ENTRY 32 HBMC_CH5_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH5_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH5_CFG_WCQ_LWM 8 HBMC_CH5_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH5_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH5_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH5_CFG_PC0_CMD2WDQS 2 HBMC_CH5_CFG_PC1_CMD2WDQS 3 HBMC_CH5_CFG_PC0_CMD2DATAOE 3 HBMC_CH5_CFG_PC1_CMD2DATAOE 4 HBMC_CH5_CFG_CB_MAJOR_MODE_EN enable HBMC_CH5_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH5_CFG_RFSH_ALL_EN enable HBMC_CH5_CFG_RFSH_PB_EN disable HBMC_CH5_CFG_USER_RFSH_PB_EN enable HBMC_CH5_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH5_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH5_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH5_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH5_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH5_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH5_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH5_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH5_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH5_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH5_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH5_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH5_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH5_CFG_TEMP_FILTER_EN enable HBMC_CH5_CFG_CATTRIP_FILTER_EN enable HBMC_CH5_CFG_CB_BYPASS_CATTRIP disable HBMC_CH5_CFG_CB_TEMP_SELECT disable HBMC_CH5_CFG_F2C_TEMP_UPDATE disable HBMC_CH5_CFG_F2C_TEMP 3 HBMC_CH5_CFG_ADDR_SCR none HBMC_CH5_CFG_ADDR_SPRD disable HBMC_CH5_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH5_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH5_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH5_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH5_CFG_CB_DEPENDENCY_MODE enable HBMC_CH5_CFG_MECC_EN disable HBMC_CH5_CFG_CA_PAR_EN enable HBMC_CH5_CFG_WR_PAR_EN enable HBMC_CH5_CFG_RD_PAR_EN enable HBMC_CH5_CFG_WR_DM_EN enable HBMC_CH5_CFG_RD_DM_EN disable HBMC_CH5_CFG_POWER_DOWN_EN enable HBMC_CH5_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH5_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH5_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH5_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH5_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH5_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH5_CFG_SELF_RFSH_EN enable HBMC_CH5_H0_FR_CLK_STCFG_EN disable HBMC_CH5_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH5_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH5_CFG_HBMC_CORECLK_PROG_DELAY1 255 HBMC_CH5_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH5_CFG_HBMCPTRENSYNCSEL enable HBMC_CH5_CFG_UB48MODE enable HBMC_CH5_CFG_HBMCH2CPTRSTART 6 HBMC_CH5_CFG_DWORD_LPBKEN disable HBMC_CH5_CFG_AWORD_LPBEN disable HBMC_CH5_CFG_DWORD_LPBKSEL disable HBMC_CH5_CFG_AWORD_LPBKSEL 0 HBMC_CH5_CFG_OBSGRPSEL 0 HBMC_CH5_CFG_OBSSIGSEL 0 HBMC_CH5_CFG_MEM_MCE disable HBMC_CH5_CFG_MEM_WA 6 HBMC_CH5_CFG_MEM_RMCE 1 HBMC_CH5_CFG_MEM_WMCE 1 HBMC_CH5_CFG_MEM_WPULSE 2 HBMC_CH5_CFG_SRAM_ECC_ENABLE enable HBMC_CH5_CFG_PC0_SRAM_INJD disable HBMC_CH5_CFG_PC0_SRAM_INJS disable HBMC_CH5_CFG_PC1_SRAM_INJD disable HBMC_CH5_CFG_PC1_SRAM_INJS disable HBMC_CH5_CFG_SRAM_SERRINTEN enable HBMC_CH5_CFG_SRAM_SLVERR_DIS disable HBMC_CH5_MMR_USER_TRIGGER disable HBMC_CH5_MMR_USER_RDWR disable HBMC_CH5_MMR_USER_BYTEENABLE 0 HBMC_CH5_MMR_USER_ADDR 0 HBMC_CH5_MMR_USER_WRDATA 0 HBMC_CH5_MMR_SBOWN_REQ disable HBMC_CH5_MMR_SBOWN_DELAY 100 HBMC_CH5_CFG_SKETCH1 3 HBMC_CH5_CFG_SKETCH2 0 HBMC_CH5_CFG_TST_PATTERN 0 HBMC_CH5_CFG_TST_START_ADDR 0 HBMC_CH5_CFG_TST_BURST_LEN 0 HBMC_CH5_CFG_TST_GEN_CMD 0 HBMC_CH5_CFG_AXI_TRAFFIC_SEL disable HBMC_CH5_CFG_TST_PC_SEL disable HBMC_CH5_CFG_TST_TRIGGER disable HBMC_CH5_CFG_TST_TIME_OUT 0 HBMC_CH5_HBMC_RATE 2 HBMC_CH5_HBM_TRFCSB 128 HBMC_CH5_HBM_TRREFD 7 HBMC_CH5_UFI_TRDEN 23 HBMC_CH5_CFG_HBMC_PC0_WTP 10 HBMC_CH5_CFG_HBMC_PC1_WTP 10 HBMC_CH5_CFG_HBMC_PC0_ITP 19 HBMC_CH5_CFG_HBMC_PC1_ITP 19 HBMC_CH5_CFG_HBMC_PC0_RTP 2 HBMC_CH5_CFG_HBMC_PC1_RTP 2 HBMC_CH5_CFG_PAR_LAT 1 HBMC_CH5_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH5_CFG_HBMC_PC0_ATI 13 HBMC_CH5_CFG_HBMC_PC0_ITI 19 HBMC_CH5_CFG_HBMC_PC0_ATA 19 HBMC_CH5_CFG_HBMC_PC0_ITA 25 HBMC_CH5_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH5_CFG_HBMC_PC0_ATP 13 HBMC_CH5_CFG_HBMC_PC0_ATR 6 HBMC_CH5_CFG_HBMC_PC0_ITR 12 HBMC_CH5_CFG_HBMC_PC0_ATW 5 HBMC_CH5_CFG_HBMC_PC0_ITW 10 HBMC_CH5_CFG_HBMC_PC0_PTA 5 HBMC_CH5_CFG_HBMC_PC0_WTI 9 HBMC_CH5_CFG_HBMC_PC0_RTA 7 HBMC_CH5_CFG_HBMC_PC0_WTA 15 HBMC_CH5_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH5_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH5_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH5_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH5_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH5_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH5_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH5_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH5_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH5_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH5_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH5_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH5_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH5_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH5_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH5_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH5_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH5_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH5_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH5_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH5_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH5_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH5_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH5_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH5_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH5_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH5_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH5_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH5_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH5_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH5_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH5_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH5_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH5_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH5_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH5_CFG_HBMC_PC1_ATI 13 HBMC_CH5_CFG_HBMC_PC1_ITI 19 HBMC_CH5_CFG_HBMC_PC1_ATA 19 HBMC_CH5_CFG_HBMC_PC1_ITA 25 HBMC_CH5_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH5_CFG_HBMC_PC1_ATP 13 HBMC_CH5_CFG_HBMC_PC1_ATR 5 HBMC_CH5_CFG_HBMC_PC1_ITR 11 HBMC_CH5_CFG_HBMC_PC1_ATW 5 HBMC_CH5_CFG_HBMC_PC1_ITW 9 HBMC_CH5_CFG_HBMC_PC1_PTA 5 HBMC_CH5_CFG_HBMC_PC1_WTI 10 HBMC_CH5_CFG_HBMC_PC1_RTA 8 HBMC_CH5_CFG_HBMC_PC1_WTA 16 HBMC_CH5_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH5_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH5_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH5_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH5_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH5_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH5_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH5_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH5_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH5_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH5_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH5_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH5_CFG_PSEUDO_BL8_EN disable HBMC_CH5_CFG_CB_WREADY_GATE_EN disable HBMC_CH5_CFG_PC0_RDEN_ON 5 HBMC_CH5_CFG_PC1_RDEN_ON 5 HBMC_CH5_CFG_PC0_RDIE_ON 9 HBMC_CH5_CFG_PC1_RDIE_ON 9 HBMC_CH5_CFG_PC0_CMD2RD 30 HBMC_CH5_CFG_PC1_CMD2RD 31 HBMC_CH5_CFG_PC0_CMD2RDPAR 31 HBMC_CH5_CFG_PC1_CMD2RDPAR 32 HBMC_CH5_CFG_PC0_WDQS_ON 4 HBMC_CH5_CFG_PC1_WDQS_ON 4 HBMC_CH5_CFG_WCQ_HWM 24 HBMC_CH5_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH5_CFG_THROTTLE_EN enable HBMC_CH5_CFG_TEMP000_ON_TIME 0 HBMC_CH5_CFG_TEMP001_ON_TIME 0 HBMC_CH5_CFG_TEMP010_ON_TIME 127 HBMC_CH5_CFG_TEMP011_ON_TIME 0 HBMC_CH5_CFG_TEMP100_ON_TIME 0 HBMC_CH5_CFG_TEMP101_ON_TIME 0 HBMC_CH5_CFG_TEMP110_ON_TIME 127 HBMC_CH5_CFG_TEMP111_ON_TIME 127 HBMC_CH5_CFG_TEMP000_OFF_TIME 255 HBMC_CH5_CFG_TEMP001_OFF_TIME 255 HBMC_CH5_CFG_TEMP010_OFF_TIME 127 HBMC_CH5_CFG_TEMP011_OFF_TIME 255 HBMC_CH5_CFG_TEMP100_OFF_TIME 255 HBMC_CH5_CFG_TEMP101_OFF_TIME 255 HBMC_CH5_CFG_TEMP110_OFF_TIME 127 HBMC_CH5_CFG_TEMP111_OFF_TIME 127 HBMC_CH5_CFG_RMW_EN disable HBMC_CH5_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH5_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH5_CFG_HBMCC2HPTRDLY 0 HBMC_CH5_HBM_TCCDL_BL4 4 HBMC_CH5_HBM_TRTW 15 HBMC_CH5_HBM_TFAW 16 HBMC_CH5_HBM_TEAW 24 HBMC_CH5_CFG_HBMC_PC0_FAW 5 HBMC_CH5_CFG_HBMC_PC0_RTI 1 HBMC_CH5_CFG_HBMC_PC0_RTW 13 HBMC_CH5_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH5_CFG_HBMC_PC1_FAW 5 HBMC_CH5_CFG_HBMC_PC1_RTI 2 HBMC_CH5_CFG_HBMC_PC1_RTW 13 HBMC_CH5_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH5_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH5_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH6_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH6_HBM_TRRDL 4 HBMC_CH6_HBM_TRCDRD 12 HBMC_CH6_HBM_TRCDWR 8 HBMC_CH6_HBM_TRTPL_BL4 5 HBMC_CH6_HBM_TRTPS_BL4 4 HBMC_CH6_HBM_TRP 12 HBMC_CH6_HBM_TCCDS_BL4 2 HBMC_CH6_HBM_TCCDR 3 HBMC_CH6_HBM_TWR 13 HBMC_CH6_HBM_TWTRL 7 HBMC_CH6_HBM_TWTRS 3 HBMC_CH6_HBM_TDQSS_MAX_PS 200 HBMC_CH6_HBM_TDQSS_MIN_PS 200 HBMC_CH6_HBM_TDQSCK_MAX_PS 3500 HBMC_CH6_HBM_TDQSQ_MAX_PS 105 HBMC_CH6_HBM_PARAM_TYPE hbm_param_min HBMC_CH6_RFSH_POLICY rfsh_policy_flexible HBMC_CH6_HBM_TREFI 3120 HBMC_CH6_HBM_TCKSRE 8 HBMC_CH6_HBM_TCKSRX 8 HBMC_CH6_HBM_TXS 216 HBMC_CH6_HBM_TCKESR 7 HBMC_CH6_HBM_TXP 6 HBMC_CH6_HBM_TPD 6 HBMC_CH6_CFG_HBMC_MODES prod HBMC_CH6_CORE_CLOCK_MHZ 350 HBMC_CH6_CORE_CLOCK_PS 1000 HBMC_CH6_CFG_CHANNEL_EN enable HBMC_CH6_CFG_TR_ORDER enable HBMC_CH6_CFG_ADDR_ORDER bgrbc HBMC_CH6_CFG_USER_RD_AP_POL rdap_hint HBMC_CH6_CFG_USER_WR_AP_POL wrap_hint HBMC_CH6_CFG_RID_DEPENDENCY_EN enable HBMC_CH6_CFG_HBMC_TX_BYPASS disable HBMC_CH6_CFG_HBMC_RX_BYPASS disable HBMC_CH6_CFG_P2HPEMUEN 2 HBMC_CH6_CFG_RMPTREN disable HBMC_CH6_CFG_RMPTRENDLY00 9 HBMC_CH6_CFG_RMPTRENDLY01 8 HBMC_CH6_CFG_RMPTRENDLY02 7 HBMC_CH6_CFG_RMPTRENDLY03 6 HBMC_CH6_CFG_RMPTRENDLY04 5 HBMC_CH6_HBM_TRAS 27 HBMC_CH6_HBM_TRRDS 4 HBMC_CH6_HBMC_OFFSET 1 HBMC_CH6_HBMC_RATE_VALUE rate_half HBMC_CH6_HBM_CLOCK_MHZ 800 HBMC_CH6_HBM_CLOCK_PS 1250 HBMC_CH6_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH6_HBM_TRFC 208 HBMC_CH6_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH6_EXT_RDIE 2 HBMC_CH6_TEMP000_THROTTLE_RATIO 0 HBMC_CH6_TEMP001_THROTTLE_RATIO 0 HBMC_CH6_TEMP010_THROTTLE_RATIO 50 HBMC_CH6_TEMP011_THROTTLE_RATIO 0 HBMC_CH6_TEMP100_THROTTLE_RATIO 0 HBMC_CH6_TEMP101_THROTTLE_RATIO 0 HBMC_CH6_TEMP110_THROTTLE_RATIO 50 HBMC_CH6_TEMP111_THROTTLE_RATIO 50 HBMC_CH6_CORE_CLK_MODE hr_asyn HBMC_CH6_CFG_HBMC_BL 4 HBMC_CH6_USER_STRB_EN enable HBMC_CH6_CFG_TBHMCRSTMIN 0 HBMC_CH6_CFG_RESET_COUNT 0 HBMC_CH6_CFG_HBMC_PC0_WL 6 HBMC_CH6_CFG_HBMC_PC0_RL 18 HBMC_CH6_CFG_HBMC_PC1_WL 6 HBMC_CH6_CFG_HBMC_PC1_RL 18 HBMC_CH6_CFG_POSTCAL_STATE sr HBMC_CH6_CFG_UFIC2PDLY 0 HBMC_CH6_CFG_UFIP2CDLY 0 HBMC_CH6_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH6_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH6_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH6_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH6_CFG_HBMC_PC0_SCR_EN enable HBMC_CH6_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH6_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH6_CFG_HBMC_PC1_SCR_EN enable HBMC_CH6_CFG_FLIP_MODE enable HBMC_CH6_CFG_DENSITY 1 HBMC_CH6_CFG_USER_DATA_WIDTH b256 HBMC_CH6_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH6_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH6_CFG_CB_RVALID_GATE_EN enable HBMC_CH6_CFG_CB_BVALID_GATE_EN enable HBMC_CH6_CFG_ADDRCHNLMUXEN disable HBMC_CH6_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH6_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH6_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH6_CFG_RCQ_AGE_LIMIT 32 HBMC_CH6_CFG_RDB_RSVD_ENTRY 0 HBMC_CH6_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH6_CFG_PC0_CMD2RDEN 15 HBMC_CH6_CFG_PC1_CMD2RDEN 16 HBMC_CH6_CFG_PC0_CMD2RDIE 13 HBMC_CH6_CFG_PC1_CMD2RDIE 14 HBMC_CH6_CFG_PC0_DATAOE_ON 2 HBMC_CH6_CFG_PC1_DATAOE_ON 2 HBMC_CH6_CFG_PC0_CMD2DATA 3 HBMC_CH6_CFG_PC1_CMD2DATA 4 HBMC_CH6_CFG_WDB_RSVD_ENTRY 32 HBMC_CH6_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH6_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH6_CFG_WCQ_LWM 8 HBMC_CH6_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH6_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH6_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH6_CFG_PC0_CMD2WDQS 2 HBMC_CH6_CFG_PC1_CMD2WDQS 3 HBMC_CH6_CFG_PC0_CMD2DATAOE 3 HBMC_CH6_CFG_PC1_CMD2DATAOE 4 HBMC_CH6_CFG_CB_MAJOR_MODE_EN enable HBMC_CH6_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH6_CFG_RFSH_ALL_EN enable HBMC_CH6_CFG_RFSH_PB_EN disable HBMC_CH6_CFG_USER_RFSH_PB_EN enable HBMC_CH6_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH6_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH6_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH6_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH6_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH6_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH6_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH6_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH6_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH6_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH6_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH6_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH6_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH6_CFG_TEMP_FILTER_EN enable HBMC_CH6_CFG_CATTRIP_FILTER_EN enable HBMC_CH6_CFG_CB_BYPASS_CATTRIP disable HBMC_CH6_CFG_CB_TEMP_SELECT disable HBMC_CH6_CFG_F2C_TEMP_UPDATE disable HBMC_CH6_CFG_F2C_TEMP 3 HBMC_CH6_CFG_ADDR_SCR none HBMC_CH6_CFG_ADDR_SPRD disable HBMC_CH6_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH6_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH6_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH6_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH6_CFG_CB_DEPENDENCY_MODE enable HBMC_CH6_CFG_MECC_EN disable HBMC_CH6_CFG_CA_PAR_EN enable HBMC_CH6_CFG_WR_PAR_EN enable HBMC_CH6_CFG_RD_PAR_EN enable HBMC_CH6_CFG_WR_DM_EN enable HBMC_CH6_CFG_RD_DM_EN disable HBMC_CH6_CFG_POWER_DOWN_EN enable HBMC_CH6_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH6_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH6_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH6_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH6_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH6_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH6_CFG_SELF_RFSH_EN enable HBMC_CH6_H0_FR_CLK_STCFG_EN disable HBMC_CH6_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH6_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH6_CFG_HBMC_CORECLK_PROG_DELAY1 63 HBMC_CH6_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH6_CFG_HBMCPTRENSYNCSEL enable HBMC_CH6_CFG_UB48MODE enable HBMC_CH6_CFG_HBMCH2CPTRSTART 6 HBMC_CH6_CFG_DWORD_LPBKEN disable HBMC_CH6_CFG_AWORD_LPBEN disable HBMC_CH6_CFG_DWORD_LPBKSEL disable HBMC_CH6_CFG_AWORD_LPBKSEL 0 HBMC_CH6_CFG_OBSGRPSEL 0 HBMC_CH6_CFG_OBSSIGSEL 0 HBMC_CH6_CFG_MEM_MCE disable HBMC_CH6_CFG_MEM_WA 6 HBMC_CH6_CFG_MEM_RMCE 1 HBMC_CH6_CFG_MEM_WMCE 1 HBMC_CH6_CFG_MEM_WPULSE 2 HBMC_CH6_CFG_SRAM_ECC_ENABLE enable HBMC_CH6_CFG_PC0_SRAM_INJD disable HBMC_CH6_CFG_PC0_SRAM_INJS disable HBMC_CH6_CFG_PC1_SRAM_INJD disable HBMC_CH6_CFG_PC1_SRAM_INJS disable HBMC_CH6_CFG_SRAM_SERRINTEN enable HBMC_CH6_CFG_SRAM_SLVERR_DIS disable HBMC_CH6_MMR_USER_TRIGGER disable HBMC_CH6_MMR_USER_RDWR disable HBMC_CH6_MMR_USER_BYTEENABLE 0 HBMC_CH6_MMR_USER_ADDR 0 HBMC_CH6_MMR_USER_WRDATA 0 HBMC_CH6_MMR_SBOWN_REQ disable HBMC_CH6_MMR_SBOWN_DELAY 100 HBMC_CH6_CFG_SKETCH1 3 HBMC_CH6_CFG_SKETCH2 0 HBMC_CH6_CFG_TST_PATTERN 0 HBMC_CH6_CFG_TST_START_ADDR 0 HBMC_CH6_CFG_TST_BURST_LEN 0 HBMC_CH6_CFG_TST_GEN_CMD 0 HBMC_CH6_CFG_AXI_TRAFFIC_SEL disable HBMC_CH6_CFG_TST_PC_SEL disable HBMC_CH6_CFG_TST_TRIGGER disable HBMC_CH6_CFG_TST_TIME_OUT 0 HBMC_CH6_HBMC_RATE 2 HBMC_CH6_HBM_TRFCSB 128 HBMC_CH6_HBM_TRREFD 7 HBMC_CH6_UFI_TRDEN 23 HBMC_CH6_CFG_HBMC_PC0_WTP 10 HBMC_CH6_CFG_HBMC_PC1_WTP 10 HBMC_CH6_CFG_HBMC_PC0_ITP 19 HBMC_CH6_CFG_HBMC_PC1_ITP 19 HBMC_CH6_CFG_HBMC_PC0_RTP 2 HBMC_CH6_CFG_HBMC_PC1_RTP 2 HBMC_CH6_CFG_PAR_LAT 1 HBMC_CH6_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH6_CFG_HBMC_PC0_ATI 13 HBMC_CH6_CFG_HBMC_PC0_ITI 19 HBMC_CH6_CFG_HBMC_PC0_ATA 19 HBMC_CH6_CFG_HBMC_PC0_ITA 25 HBMC_CH6_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH6_CFG_HBMC_PC0_ATP 13 HBMC_CH6_CFG_HBMC_PC0_ATR 6 HBMC_CH6_CFG_HBMC_PC0_ITR 12 HBMC_CH6_CFG_HBMC_PC0_ATW 5 HBMC_CH6_CFG_HBMC_PC0_ITW 10 HBMC_CH6_CFG_HBMC_PC0_PTA 5 HBMC_CH6_CFG_HBMC_PC0_WTI 9 HBMC_CH6_CFG_HBMC_PC0_RTA 7 HBMC_CH6_CFG_HBMC_PC0_WTA 15 HBMC_CH6_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH6_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH6_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH6_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH6_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH6_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH6_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH6_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH6_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH6_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH6_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH6_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH6_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH6_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH6_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH6_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH6_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH6_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH6_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH6_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH6_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH6_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH6_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH6_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH6_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH6_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH6_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH6_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH6_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH6_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH6_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH6_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH6_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH6_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH6_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH6_CFG_HBMC_PC1_ATI 13 HBMC_CH6_CFG_HBMC_PC1_ITI 19 HBMC_CH6_CFG_HBMC_PC1_ATA 19 HBMC_CH6_CFG_HBMC_PC1_ITA 25 HBMC_CH6_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH6_CFG_HBMC_PC1_ATP 13 HBMC_CH6_CFG_HBMC_PC1_ATR 5 HBMC_CH6_CFG_HBMC_PC1_ITR 11 HBMC_CH6_CFG_HBMC_PC1_ATW 5 HBMC_CH6_CFG_HBMC_PC1_ITW 9 HBMC_CH6_CFG_HBMC_PC1_PTA 5 HBMC_CH6_CFG_HBMC_PC1_WTI 10 HBMC_CH6_CFG_HBMC_PC1_RTA 8 HBMC_CH6_CFG_HBMC_PC1_WTA 16 HBMC_CH6_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH6_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH6_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH6_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH6_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH6_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH6_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH6_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH6_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH6_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH6_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH6_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH6_CFG_PSEUDO_BL8_EN disable HBMC_CH6_CFG_CB_WREADY_GATE_EN disable HBMC_CH6_CFG_PC0_RDEN_ON 5 HBMC_CH6_CFG_PC1_RDEN_ON 5 HBMC_CH6_CFG_PC0_RDIE_ON 9 HBMC_CH6_CFG_PC1_RDIE_ON 9 HBMC_CH6_CFG_PC0_CMD2RD 30 HBMC_CH6_CFG_PC1_CMD2RD 31 HBMC_CH6_CFG_PC0_CMD2RDPAR 31 HBMC_CH6_CFG_PC1_CMD2RDPAR 32 HBMC_CH6_CFG_PC0_WDQS_ON 4 HBMC_CH6_CFG_PC1_WDQS_ON 4 HBMC_CH6_CFG_WCQ_HWM 24 HBMC_CH6_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH6_CFG_THROTTLE_EN enable HBMC_CH6_CFG_TEMP000_ON_TIME 0 HBMC_CH6_CFG_TEMP001_ON_TIME 0 HBMC_CH6_CFG_TEMP010_ON_TIME 127 HBMC_CH6_CFG_TEMP011_ON_TIME 0 HBMC_CH6_CFG_TEMP100_ON_TIME 0 HBMC_CH6_CFG_TEMP101_ON_TIME 0 HBMC_CH6_CFG_TEMP110_ON_TIME 127 HBMC_CH6_CFG_TEMP111_ON_TIME 127 HBMC_CH6_CFG_TEMP000_OFF_TIME 255 HBMC_CH6_CFG_TEMP001_OFF_TIME 255 HBMC_CH6_CFG_TEMP010_OFF_TIME 127 HBMC_CH6_CFG_TEMP011_OFF_TIME 255 HBMC_CH6_CFG_TEMP100_OFF_TIME 255 HBMC_CH6_CFG_TEMP101_OFF_TIME 255 HBMC_CH6_CFG_TEMP110_OFF_TIME 127 HBMC_CH6_CFG_TEMP111_OFF_TIME 127 HBMC_CH6_CFG_RMW_EN disable HBMC_CH6_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH6_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH6_CFG_HBMCC2HPTRDLY 0 HBMC_CH6_HBM_TCCDL_BL4 4 HBMC_CH6_HBM_TRTW 15 HBMC_CH6_HBM_TFAW 16 HBMC_CH6_HBM_TEAW 24 HBMC_CH6_CFG_HBMC_PC0_FAW 5 HBMC_CH6_CFG_HBMC_PC0_RTI 1 HBMC_CH6_CFG_HBMC_PC0_RTW 13 HBMC_CH6_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH6_CFG_HBMC_PC1_FAW 5 HBMC_CH6_CFG_HBMC_PC1_RTI 2 HBMC_CH6_CFG_HBMC_PC1_RTW 13 HBMC_CH6_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH6_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH6_CFG_ARFIFO_RSVD_ENTRY 24 HBMC_CH7_HBM_DEVICE hbm_device_4gb_4hi HBMC_CH7_HBM_TRRDL 4 HBMC_CH7_HBM_TRCDRD 12 HBMC_CH7_HBM_TRCDWR 8 HBMC_CH7_HBM_TRTPL_BL4 5 HBMC_CH7_HBM_TRTPS_BL4 4 HBMC_CH7_HBM_TRP 12 HBMC_CH7_HBM_TCCDS_BL4 2 HBMC_CH7_HBM_TCCDR 3 HBMC_CH7_HBM_TWR 13 HBMC_CH7_HBM_TWTRL 7 HBMC_CH7_HBM_TWTRS 3 HBMC_CH7_HBM_TDQSS_MAX_PS 200 HBMC_CH7_HBM_TDQSS_MIN_PS 200 HBMC_CH7_HBM_TDQSCK_MAX_PS 3500 HBMC_CH7_HBM_TDQSQ_MAX_PS 105 HBMC_CH7_HBM_PARAM_TYPE hbm_param_min HBMC_CH7_RFSH_POLICY rfsh_policy_flexible HBMC_CH7_HBM_TREFI 3120 HBMC_CH7_HBM_TCKSRE 8 HBMC_CH7_HBM_TCKSRX 8 HBMC_CH7_HBM_TXS 216 HBMC_CH7_HBM_TCKESR 7 HBMC_CH7_HBM_TXP 6 HBMC_CH7_HBM_TPD 6 HBMC_CH7_CFG_HBMC_MODES prod HBMC_CH7_CORE_CLOCK_MHZ 350 HBMC_CH7_CORE_CLOCK_PS 1000 HBMC_CH7_CFG_CHANNEL_EN enable HBMC_CH7_CFG_TR_ORDER enable HBMC_CH7_CFG_ADDR_ORDER bgrbc HBMC_CH7_CFG_USER_RD_AP_POL rdap_hint HBMC_CH7_CFG_USER_WR_AP_POL wrap_hint HBMC_CH7_CFG_RID_DEPENDENCY_EN enable HBMC_CH7_CFG_HBMC_TX_BYPASS disable HBMC_CH7_CFG_HBMC_RX_BYPASS disable HBMC_CH7_CFG_P2HPEMUEN 2 HBMC_CH7_CFG_RMPTREN disable HBMC_CH7_CFG_RMPTRENDLY00 9 HBMC_CH7_CFG_RMPTRENDLY01 8 HBMC_CH7_CFG_RMPTRENDLY02 7 HBMC_CH7_CFG_RMPTRENDLY03 6 HBMC_CH7_CFG_RMPTRENDLY04 5 HBMC_CH7_HBM_TRAS 27 HBMC_CH7_HBM_TRRDS 4 HBMC_CH7_HBMC_OFFSET 1 HBMC_CH7_HBMC_RATE_VALUE rate_half HBMC_CH7_HBM_CLOCK_MHZ 800 HBMC_CH7_HBM_CLOCK_PS 1250 HBMC_CH7_RFSH_MODE rfsh_mode_ctrl_rfsh_all HBMC_CH7_HBM_TRFC 208 HBMC_CH7_DATA_WIDTH_MODE data_width_mode_sdw HBMC_CH7_EXT_RDIE 2 HBMC_CH7_TEMP000_THROTTLE_RATIO 0 HBMC_CH7_TEMP001_THROTTLE_RATIO 0 HBMC_CH7_TEMP010_THROTTLE_RATIO 50 HBMC_CH7_TEMP011_THROTTLE_RATIO 0 HBMC_CH7_TEMP100_THROTTLE_RATIO 0 HBMC_CH7_TEMP101_THROTTLE_RATIO 0 HBMC_CH7_TEMP110_THROTTLE_RATIO 50 HBMC_CH7_TEMP111_THROTTLE_RATIO 50 HBMC_CH7_CORE_CLK_MODE hr_asyn HBMC_CH7_CFG_HBMC_BL 4 HBMC_CH7_USER_STRB_EN enable HBMC_CH7_CFG_TBHMCRSTMIN 0 HBMC_CH7_CFG_RESET_COUNT 0 HBMC_CH7_CFG_HBMC_PC0_WL 6 HBMC_CH7_CFG_HBMC_PC0_RL 18 HBMC_CH7_CFG_HBMC_PC1_WL 6 HBMC_CH7_CFG_HBMC_PC1_RL 18 HBMC_CH7_CFG_POSTCAL_STATE sr HBMC_CH7_CFG_UFIC2PDLY 0 HBMC_CH7_CFG_UFIP2CDLY 0 HBMC_CH7_CFG_CB_RMW_RD_IDLE_WAIT_EN disable HBMC_CH7_CFG_CB_RMW_FIFO_EMPTY_WAIT_EN disable HBMC_CH7_CFG_SB_POST_UPDATE_CYCLE 1 HBMC_CH7_CFG_HBMC_PC0_SCR_SEEDSEL 0 HBMC_CH7_CFG_HBMC_PC0_SCR_EN enable HBMC_CH7_CFG_HBMC_RFSH_PB_BURST_GAP 1 HBMC_CH7_CFG_HBMC_PC1_SCR_SEEDSEL 0 HBMC_CH7_CFG_HBMC_PC1_SCR_EN enable HBMC_CH7_CFG_FLIP_MODE enable HBMC_CH7_CFG_DENSITY 1 HBMC_CH7_CFG_USER_DATA_WIDTH b256 HBMC_CH7_CFG_CB_BREADY_BYPASS_EN disable HBMC_CH7_CFG_CB_RREADY_BYPASS_EN disable HBMC_CH7_CFG_CB_RVALID_GATE_EN enable HBMC_CH7_CFG_CB_BVALID_GATE_EN enable HBMC_CH7_CFG_ADDRCHNLMUXEN disable HBMC_CH7_CFG_AXI_CMD_DEMUX_EN disable HBMC_CH7_CFG_PC0_MAJOR_MODE_UPDATE_CNT disable HBMC_CH7_CFG_PC1_MAJOR_MODE_UPDATE_CNT disable HBMC_CH7_CFG_RCQ_AGE_LIMIT 32 HBMC_CH7_CFG_RDB_RSVD_ENTRY 0 HBMC_CH7_CFG_RD_STRB_IDLE_THRESHOLD 50 HBMC_CH7_CFG_PC0_CMD2RDEN 15 HBMC_CH7_CFG_PC1_CMD2RDEN 16 HBMC_CH7_CFG_PC0_CMD2RDIE 13 HBMC_CH7_CFG_PC1_CMD2RDIE 14 HBMC_CH7_CFG_PC0_DATAOE_ON 2 HBMC_CH7_CFG_PC1_DATAOE_ON 2 HBMC_CH7_CFG_PC0_CMD2DATA 3 HBMC_CH7_CFG_PC1_CMD2DATA 4 HBMC_CH7_CFG_WDB_RSVD_ENTRY 32 HBMC_CH7_CFG_AWDB_RSVD_ENTRY 32 HBMC_CH7_CFG_WCQ_BURST_THRESHOLD 64 HBMC_CH7_CFG_WCQ_LWM 8 HBMC_CH7_CFG_WCQ_TIMEOUT_THRESHOLD 64 HBMC_CH7_CFG_PC0_MAJOR_MODE_UPDATE_CFG disable HBMC_CH7_CFG_PC1_MAJOR_MODE_UPDATE_CFG disable HBMC_CH7_CFG_PC0_CMD2WDQS 2 HBMC_CH7_CFG_PC1_CMD2WDQS 3 HBMC_CH7_CFG_PC0_CMD2DATAOE 3 HBMC_CH7_CFG_PC1_CMD2DATAOE 4 HBMC_CH7_CFG_CB_MAJOR_MODE_EN enable HBMC_CH7_CFG_CB_STRICT_MAJOR_MODE_EN enable HBMC_CH7_CFG_RFSH_ALL_EN enable HBMC_CH7_CFG_RFSH_PB_EN disable HBMC_CH7_CFG_USER_RFSH_PB_EN enable HBMC_CH7_CFG_RFSH_AB_TO_PB_EN enable HBMC_CH7_CFG_CB_TEMP_RFSH_FILTER_EN disable HBMC_CH7_CFG_RFSH_POST_LOWER_LIMIT 1 HBMC_CH7_CFG_RFSH_PRE_UPPER_LIMIT 1 HBMC_CH7_CFG_RFSH_IDLE_THRESHOLD 20 HBMC_CH7_CFG_TEMP000_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH7_CFG_TEMP001_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH7_CFG_TEMP011_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH7_CFG_TEMP010_NO_OF_RFSH_BEFORE_SELF_RFSH 2 HBMC_CH7_CFG_TEMP110_NO_OF_RFSH_BEFORE_SELF_RFSH 4 HBMC_CH7_CFG_TEMP111_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH7_CFG_TEMP101_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH7_CFG_TEMP100_NO_OF_RFSH_BEFORE_SELF_RFSH 1 HBMC_CH7_CFG_TEMP_FILTER_EN enable HBMC_CH7_CFG_CATTRIP_FILTER_EN enable HBMC_CH7_CFG_CB_BYPASS_CATTRIP disable HBMC_CH7_CFG_CB_TEMP_SELECT disable HBMC_CH7_CFG_F2C_TEMP_UPDATE disable HBMC_CH7_CFG_F2C_TEMP 3 HBMC_CH7_CFG_ADDR_SCR none HBMC_CH7_CFG_ADDR_SPRD disable HBMC_CH7_CFG_CB_RD_COL_ARB_PRIORITY_EN enable HBMC_CH7_CFG_CB_WR_COL_ARB_PRIORITY_EN enable HBMC_CH7_CFG_CB_RD_ROW_ARB_PRIORITY_EN enable HBMC_CH7_CFG_CB_WR_ROW_ARB_PRIORITY_EN enable HBMC_CH7_CFG_CB_DEPENDENCY_MODE enable HBMC_CH7_CFG_MECC_EN disable HBMC_CH7_CFG_CA_PAR_EN enable HBMC_CH7_CFG_WR_PAR_EN enable HBMC_CH7_CFG_RD_PAR_EN enable HBMC_CH7_CFG_WR_DM_EN enable HBMC_CH7_CFG_RD_DM_EN disable HBMC_CH7_CFG_POWER_DOWN_EN enable HBMC_CH7_CFG_POWER_DOWN_CK_DIS_EN disable HBMC_CH7_CFG_AUTO_RD_POWER_DOWN_EXIT_EN enable HBMC_CH7_CFG_AUTO_WR_POWER_DOWN_EXIT_EN enable HBMC_CH7_CFG_AUTO_RD_SELF_RFSH_EXIT_EN enable HBMC_CH7_CFG_AUTO_WR_SELF_RFSH_EXIT_EN enable HBMC_CH7_CFG_SELF_RFSH_CK_DIS_EN enable HBMC_CH7_CFG_SELF_RFSH_EN enable HBMC_CH7_H0_FR_CLK_STCFG_EN disable HBMC_CH7_CFG_SB_PRE_STALL_CYCLE 3 HBMC_CH7_CFG_SB_POST_STALL_CYCLE 1 HBMC_CH7_CFG_HBMC_CORECLK_PROG_DELAY1 63 HBMC_CH7_CFG_HBMC_CORECLK_PROG_DELAY2 0 HBMC_CH7_CFG_HBMCPTRENSYNCSEL enable HBMC_CH7_CFG_UB48MODE enable HBMC_CH7_CFG_HBMCH2CPTRSTART 6 HBMC_CH7_CFG_DWORD_LPBKEN disable HBMC_CH7_CFG_AWORD_LPBEN disable HBMC_CH7_CFG_DWORD_LPBKSEL disable HBMC_CH7_CFG_AWORD_LPBKSEL 0 HBMC_CH7_CFG_OBSGRPSEL 0 HBMC_CH7_CFG_OBSSIGSEL 0 HBMC_CH7_CFG_MEM_MCE disable HBMC_CH7_CFG_MEM_WA 6 HBMC_CH7_CFG_MEM_RMCE 1 HBMC_CH7_CFG_MEM_WMCE 1 HBMC_CH7_CFG_MEM_WPULSE 2 HBMC_CH7_CFG_SRAM_ECC_ENABLE enable HBMC_CH7_CFG_PC0_SRAM_INJD disable HBMC_CH7_CFG_PC0_SRAM_INJS disable HBMC_CH7_CFG_PC1_SRAM_INJD disable HBMC_CH7_CFG_PC1_SRAM_INJS disable HBMC_CH7_CFG_SRAM_SERRINTEN enable HBMC_CH7_CFG_SRAM_SLVERR_DIS disable HBMC_CH7_MMR_USER_TRIGGER disable HBMC_CH7_MMR_USER_RDWR disable HBMC_CH7_MMR_USER_BYTEENABLE 0 HBMC_CH7_MMR_USER_ADDR 0 HBMC_CH7_MMR_USER_WRDATA 0 HBMC_CH7_MMR_SBOWN_REQ disable HBMC_CH7_MMR_SBOWN_DELAY 100 HBMC_CH7_CFG_SKETCH1 3 HBMC_CH7_CFG_SKETCH2 0 HBMC_CH7_CFG_TST_PATTERN 0 HBMC_CH7_CFG_TST_START_ADDR 0 HBMC_CH7_CFG_TST_BURST_LEN 0 HBMC_CH7_CFG_TST_GEN_CMD 0 HBMC_CH7_CFG_AXI_TRAFFIC_SEL disable HBMC_CH7_CFG_TST_PC_SEL disable HBMC_CH7_CFG_TST_TRIGGER disable HBMC_CH7_CFG_TST_TIME_OUT 0 HBMC_CH7_HBMC_RATE 2 HBMC_CH7_HBM_TRFCSB 128 HBMC_CH7_HBM_TRREFD 7 HBMC_CH7_UFI_TRDEN 23 HBMC_CH7_CFG_HBMC_PC0_WTP 10 HBMC_CH7_CFG_HBMC_PC1_WTP 10 HBMC_CH7_CFG_HBMC_PC0_ITP 19 HBMC_CH7_CFG_HBMC_PC1_ITP 19 HBMC_CH7_CFG_HBMC_PC0_RTP 2 HBMC_CH7_CFG_HBMC_PC1_RTP 2 HBMC_CH7_CFG_PAR_LAT 1 HBMC_CH7_CFG_HBMC_PC0_FIW_SHORT 5 HBMC_CH7_CFG_HBMC_PC0_ATI 13 HBMC_CH7_CFG_HBMC_PC0_ITI 19 HBMC_CH7_CFG_HBMC_PC0_ATA 19 HBMC_CH7_CFG_HBMC_PC0_ITA 25 HBMC_CH7_CFG_HBMC_PC0_ITA_DLY 5 HBMC_CH7_CFG_HBMC_PC0_ATP 13 HBMC_CH7_CFG_HBMC_PC0_ATR 6 HBMC_CH7_CFG_HBMC_PC0_ITR 12 HBMC_CH7_CFG_HBMC_PC0_ATW 5 HBMC_CH7_CFG_HBMC_PC0_ITW 10 HBMC_CH7_CFG_HBMC_PC0_PTA 5 HBMC_CH7_CFG_HBMC_PC0_WTI 9 HBMC_CH7_CFG_HBMC_PC0_RTA 7 HBMC_CH7_CFG_HBMC_PC0_WTA 15 HBMC_CH7_CFG_HBMC_PC0_ATA_DBG 1 HBMC_CH7_CFG_HBMC_PC0_ATI_DBG 1 HBMC_CH7_CFG_HBMC_PC0_ITA_DBG 7 HBMC_CH7_CFG_HBMC_PC0_ITI_DBG 1 HBMC_CH7_CFG_HBMC_PC0_RTRWTW_DBG 0 HBMC_CH7_CFG_HBMC_PC0_WTR_DBG 5 HBMC_CH7_CFG_HBMC_PC0_ATA_SBG 1 HBMC_CH7_CFG_HBMC_PC0_ATI_SBG 1 HBMC_CH7_CFG_HBMC_PC0_ITA_SBG 7 HBMC_CH7_CFG_HBMC_PC0_ITI_SBG 1 HBMC_CH7_CFG_HBMC_PC0_WTR_SBG 7 HBMC_CH7_CFG_HBMC_PC0_RTR_DSID 1 HBMC_CH7_CFG_HBMC_POWER_DOWN_TO_CK_DIS 5 HBMC_CH7_CFG_HBMC_CK_DIS_TO_POWER_DOWN 5 HBMC_CH7_CFG_HBMC_MIN_POWER_DOWN 4 HBMC_CH7_CFG_HBMC_POWER_DOWN_TO_VALID 4 HBMC_CH7_CFG_HBMC_SELF_RFSH_TO_CK_DIS 5 HBMC_CH7_CFG_HBMC_CK_DIS_TO_SELF_RFSH 5 HBMC_CH7_CFG_HBMC_SELF_RFSH_TO_VALID 109 HBMC_CH7_CFG_HBMC_MIN_SELF_RFSH 5 HBMC_CH7_CFG_HBMC_RFSH_AB_TO_VALID 105 HBMC_CH7_CFG_HBMC_RFSH_PB_TO_RFSH_PB 5 HBMC_CH7_CFG_HBMC_RFSH_PB_TO_VALID 65 HBMC_CH7_CFG_HBMC_TEMP000_RFSH_PERIOD 6238 HBMC_CH7_CFG_HBMC_TEMP001_RFSH_PERIOD 3118 HBMC_CH7_CFG_HBMC_TEMP011_RFSH_PERIOD 1558 HBMC_CH7_CFG_HBMC_TEMP010_RFSH_PERIOD 778 HBMC_CH7_CFG_HBMC_TEMP110_RFSH_PERIOD 388 HBMC_CH7_CFG_HBMC_TEMP111_RFSH_PERIOD 1558 HBMC_CH7_CFG_HBMC_TEMP101_RFSH_PERIOD 1558 HBMC_CH7_CFG_HBMC_TEMP100_RFSH_PERIOD 1558 HBMC_CH7_CFG_HBMC_RFSH_PB_TO_RFSH_PB_OFFSET 3 HBMC_CH7_CFG_HBMC_PCH_PB_TO_VALID 7 HBMC_CH7_CFG_HBMC_PCH_AB_TO_VALID 7 HBMC_CH7_CFG_HBMC_PC1_FIW_SHORT 5 HBMC_CH7_CFG_HBMC_PC1_ATI 13 HBMC_CH7_CFG_HBMC_PC1_ITI 19 HBMC_CH7_CFG_HBMC_PC1_ATA 19 HBMC_CH7_CFG_HBMC_PC1_ITA 25 HBMC_CH7_CFG_HBMC_PC1_ITA_DLY 5 HBMC_CH7_CFG_HBMC_PC1_ATP 13 HBMC_CH7_CFG_HBMC_PC1_ATR 5 HBMC_CH7_CFG_HBMC_PC1_ITR 11 HBMC_CH7_CFG_HBMC_PC1_ATW 5 HBMC_CH7_CFG_HBMC_PC1_ITW 9 HBMC_CH7_CFG_HBMC_PC1_PTA 5 HBMC_CH7_CFG_HBMC_PC1_WTI 10 HBMC_CH7_CFG_HBMC_PC1_RTA 8 HBMC_CH7_CFG_HBMC_PC1_WTA 16 HBMC_CH7_CFG_HBMC_PC1_ATA_DBG 1 HBMC_CH7_CFG_HBMC_PC1_ATI_DBG 1 HBMC_CH7_CFG_HBMC_PC1_ITA_DBG 7 HBMC_CH7_CFG_HBMC_PC1_ITI_DBG 1 HBMC_CH7_CFG_HBMC_PC1_RTRWTW_DBG 0 HBMC_CH7_CFG_HBMC_PC1_WTR_DBG 5 HBMC_CH7_CFG_HBMC_PC1_ATA_SBG 1 HBMC_CH7_CFG_HBMC_PC1_ATI_SBG 1 HBMC_CH7_CFG_HBMC_PC1_ITA_SBG 7 HBMC_CH7_CFG_HBMC_PC1_ITI_SBG 1 HBMC_CH7_CFG_HBMC_PC1_WTR_SBG 7 HBMC_CH7_CFG_HBMC_PC1_RTR_DSID 1 HBMC_CH7_CFG_PSEUDO_BL8_EN disable HBMC_CH7_CFG_CB_WREADY_GATE_EN disable HBMC_CH7_CFG_PC0_RDEN_ON 5 HBMC_CH7_CFG_PC1_RDEN_ON 5 HBMC_CH7_CFG_PC0_RDIE_ON 9 HBMC_CH7_CFG_PC1_RDIE_ON 9 HBMC_CH7_CFG_PC0_CMD2RD 30 HBMC_CH7_CFG_PC1_CMD2RD 31 HBMC_CH7_CFG_PC0_CMD2RDPAR 31 HBMC_CH7_CFG_PC1_CMD2RDPAR 32 HBMC_CH7_CFG_PC0_WDQS_ON 4 HBMC_CH7_CFG_PC1_WDQS_ON 4 HBMC_CH7_CFG_WCQ_HWM 24 HBMC_CH7_CFG_RFSH_POST_UPPER_LIMIT 1 HBMC_CH7_CFG_THROTTLE_EN enable HBMC_CH7_CFG_TEMP000_ON_TIME 0 HBMC_CH7_CFG_TEMP001_ON_TIME 0 HBMC_CH7_CFG_TEMP010_ON_TIME 127 HBMC_CH7_CFG_TEMP011_ON_TIME 0 HBMC_CH7_CFG_TEMP100_ON_TIME 0 HBMC_CH7_CFG_TEMP101_ON_TIME 0 HBMC_CH7_CFG_TEMP110_ON_TIME 127 HBMC_CH7_CFG_TEMP111_ON_TIME 127 HBMC_CH7_CFG_TEMP000_OFF_TIME 255 HBMC_CH7_CFG_TEMP001_OFF_TIME 255 HBMC_CH7_CFG_TEMP010_OFF_TIME 127 HBMC_CH7_CFG_TEMP011_OFF_TIME 255 HBMC_CH7_CFG_TEMP100_OFF_TIME 255 HBMC_CH7_CFG_TEMP101_OFF_TIME 255 HBMC_CH7_CFG_TEMP110_OFF_TIME 127 HBMC_CH7_CFG_TEMP111_OFF_TIME 127 HBMC_CH7_CFG_RMW_EN disable HBMC_CH7_CFG_POWER_DOWN_IDLE_THRESHOLD 1 HBMC_CH7_CFG_SB_PRE_UPDATE_CYCLE 6 HBMC_CH7_CFG_HBMCC2HPTRDLY 0 HBMC_CH7_HBM_TCCDL_BL4 4 HBMC_CH7_HBM_TRTW 15 HBMC_CH7_HBM_TFAW 16 HBMC_CH7_HBM_TEAW 24 HBMC_CH7_CFG_HBMC_PC0_FAW 5 HBMC_CH7_CFG_HBMC_PC0_RTI 1 HBMC_CH7_CFG_HBMC_PC0_RTW 13 HBMC_CH7_CFG_HBMC_PC0_RTRWTW_SBG 1 HBMC_CH7_CFG_HBMC_PC1_FAW 5 HBMC_CH7_CFG_HBMC_PC1_RTI 2 HBMC_CH7_CFG_HBMC_PC1_RTW 13 HBMC_CH7_CFG_HBMC_PC1_RTRWTW_SBG 1 HBMC_CH7_CFG_AWFIFO_RSVD_ENTRY 24 HBMC_CH7_CFG_ARFIFO_RSVD_ENTRY 24 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)