---

pcie_s10_hip_ast_0

altera_pcie_s10_hip_ast v23.0.0

Parameters interface_type_hwtcl Avalon-ST wrala_hwtcl Gen3x16, Interface - 256 bit, 500 MHz select_design_example_hwtcl PIO virtual_rp_ep_mode_hwtcl Native Endpoint enable_multi_func_hwtcl 0 pf0_bar0_type_hwtcl 64-bit prefetchable memory pf0_bar0_address_width_hwtcl 19 pf0_bar1_type_hwtcl Disabled pf0_bar1_address_width_hwtcl 0 pf0_bar2_type_hwtcl 64-bit prefetchable memory pf0_bar2_address_width_hwtcl 20 pf0_bar3_type_hwtcl Disabled pf0_bar3_address_width_hwtcl 0 pf0_bar4_type_hwtcl 64-bit prefetchable memory pf0_bar4_address_width_hwtcl 25 pf0_bar5_type_hwtcl Disabled pf0_bar5_address_width_hwtcl 0 pf0_expansion_base_address_register_hwtcl 0 pf0_sriov_vf_bar0_type_hwtcl Disabled pf0_sriov_vf_bar0_address_width_hwtcl 0 pf0_sriov_vf_bar1_type_hwtcl Disabled pf0_sriov_vf_bar1_address_width_hwtcl 0 pf0_sriov_vf_bar2_type_hwtcl Disabled pf0_sriov_vf_bar2_address_width_hwtcl 0 pf0_sriov_vf_bar3_type_hwtcl Disabled pf0_sriov_vf_bar3_address_width_hwtcl 0 pf0_sriov_vf_bar4_type_hwtcl Disabled pf0_sriov_vf_bar4_address_width_hwtcl 0 pf0_sriov_vf_bar5_type_hwtcl Disabled pf0_sriov_vf_bar5_address_width_hwtcl 0 enable_avst_reset_hwtcl 0 use_ast_parity_hwtcl 0 virtual_maxpayload_size_hwtcl 512 pf0_pcie_cap_ext_tag_supp_hwtcl 0 pf0_pcie_cap_flr_cap_user_hwtcl 1 pf0_pcie_cap_port_num_hwtcl 1 pf0_pcie_cap_slot_clk_config_hwtcl 0 virtual_pf0_msi_enable_hwtcl 0 virtual_pf1_msi_enable_hwtcl 0 virtual_pf2_msi_enable_hwtcl 0 virtual_pf3_msi_enable_hwtcl 0 pf0_pci_msi_multiple_msg_cap_hwtcl 1 virtual_pf0_msix_enable_hwtcl 0 pf0_pci_msix_table_size_hwtcl 0 pf0_pci_msix_table_offset_hwtcl 0 pf0_pci_msix_bir_hwtcl 0 pf0_pci_msix_pba_offset_hwtcl 0 pf0_pci_msix_pba_hwtcl 0 virtual_pf1_msix_enable_hwtcl 0 pf1_pci_msix_table_size_hwtcl 0 pf1_pci_msix_table_offset_hwtcl 0 pf1_pci_msix_bir_hwtcl 0 pf1_pci_msix_pba_offset_hwtcl 0 pf1_pci_msix_pba_hwtcl 0 virtual_pf2_msix_enable_hwtcl 0 pf2_pci_msix_table_size_hwtcl 0 pf2_pci_msix_table_offset_hwtcl 0 pf2_pci_msix_bir_hwtcl 0 pf2_pci_msix_pba_offset_hwtcl 0 pf2_pci_msix_pba_hwtcl 0 virtual_pf3_msix_enable_hwtcl 0 pf3_pci_msix_table_size_hwtcl 0 pf3_pci_msix_table_offset_hwtcl 0 pf3_pci_msix_bir_hwtcl 0 pf3_pci_msix_pba_offset_hwtcl 0 pf3_pci_msix_pba_hwtcl 0 pf0_pcie_slot_imp_hwtcl 0 pf0_pcie_cap_slot_power_limit_value_hwtcl 0 pf0_pcie_cap_slot_power_limit_scale_hwtcl 0 pf0_pcie_cap_phy_slot_num_hwtcl 0 pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl 0 pf0_pcie_cap_ep_l1_accpt_latency_hwtcl 0 cvp_user_id_hwtcl 4466 hip_reconfig_hwtcl 0 xcvr_reconfig_hwtcl 0 xcvr_adme_hwtcl 0 pcie_link_inspector_hwtcl 0 pf0_pcie_cap_sel_deemphasis_hwtcl 6dB anlg_voltage 1_1V pf0_pci_type0_vendor_id_hwtcl 5724 pf0_pci_type0_device_id_hwtcl 29873 pf0_revision_id_hwtcl 1 pf0_class_code_hwtcl 1114112 pf0_subsys_vendor_id_hwtcl 4466 pf0_subsys_dev_id_hwtcl 17 enable_example_design_sim_hwtcl 0 enable_example_design_synth_hwtcl 1 select_design_example_rtl_lang_hwtcl Verilog chosen_devkit_hwtcl NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pcie_s10_hip_ast_0_phy_g3x16

altera_pcie_s10_hip_ast_altera_xcvr_pcie_hip_native_s10 v23.0.0

Parameters xcvr_tile_type H-Tile anlg_voltage 1_1V rx_pma_optimal_settings true rx_pma_adapt_mode_htile ctle_dfe_mode_2 HIP_PROTOCOL_MODE pipe_g3 HIP_RECONFIG_ENABLE 1 XCVR_ADME_ENABLE 0 USED_CHANNELS 16 enable_tx_fast_pipeln_reg 1 enable_rx_fast_pipeln_reg 1 enable_debug_channels 0 split_interfaces false generate_docs 1 qsf_assignments_enable 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pcie_s10_hip_ast_0_phy_g3x16_phy_g3x16

altera_xcvr_pcie_hip_native_s10 v19.1

Parameters xcvr_tile_type H-Tile anlg_voltage 1_1V rx_pma_optimal_settings true rx_pma_adapt_mode_htile ctle_dfe_mode_2 HIP_PROTOCOL_MODE pipe_g3 HIP_RECONFIG_ENABLE 1 XCVR_ADME_ENABLE 0 USED_CHANNELS 16 enable_tx_fast_pipeln_reg 1 enable_rx_fast_pipeln_reg 1 enable_debug_channels 0 split_interfaces false generate_docs 1 qsf_assignments_enable 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pcie_s10_hip_ast_0_fpll_g3

altera_pcie_s10_hip_ast_altera_xcvr_fpll_s10_htile v23.0.0

Parameters rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 set_capability_reg_enable 0 set_user_identifier 240 set_csr_soft_logic_enable 0 rcfg_file_prefix altera_xcvr_fpll_s10 rcfg_sv_file_enable 0 rcfg_h_file_enable 0 rcfg_mif_file_enable 0 rcfg_multi_enable 0 set_rcfg_emb_strm_enable 0 rcfg_reduced_files_enable 0 rcfg_profile_cnt 2 rcfg_profile_select 1 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data7 generate_docs 0 set_primary_use 2 message_level error set_prot_mode 3 set_bw_sel high set_refclk_cnt 1 set_refclk_index 0 set_enable_hclk_out 1 set_output_clock_frequency 2500.0 output_datarate 5000.0 set_enable_fractional 0 set_auto_reference_clock_frequency 100.0 select_manual_config false set_m_counter 50 set_ref_clk_div 1 set_l_counter 2 set_power_mode 1_1V enable_mcgb 0 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 0 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 0 mcgb_in_clk_freq 2500.0 mcgb_out_datarate 5000.0 enable_bonding_clks 0 pma_width 64 set_parameter_list L-Counter,M-Counter,N-Counter,C-Counter,K-Counter,PLL output datarate,PLL output frequency,VCO frequency,PFD frequency,C0 Counter Output Frequency,C0 Counter Output Frequency in Hz,C1 Counter Output Frequency,C1 Counter Output Frequency in Hz set_parameter_values 1,1,1,1,0,5000.0,2500.0,1250.0,1250.0,0,0,0,0 set_display_units ,,,,,Mbps,MHz,MHz,MHz,ps,ps,ps,ps deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pcie_s10_hip_ast_0_fpll_g3_fpll_g3

altera_xcvr_fpll_s10_htile v19.1.2

Parameters rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 set_capability_reg_enable 0 set_user_identifier 240 set_csr_soft_logic_enable 0 rcfg_file_prefix altera_xcvr_fpll_s10 rcfg_sv_file_enable 0 rcfg_h_file_enable 0 rcfg_mif_file_enable 0 rcfg_multi_enable 0 set_rcfg_emb_strm_enable 0 rcfg_reduced_files_enable 0 rcfg_profile_cnt 2 rcfg_profile_select 1 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data7 generate_docs 0 set_primary_use 2 message_level error set_prot_mode 3 set_bw_sel high set_refclk_cnt 1 set_refclk_index 0 set_enable_hclk_out 1 set_output_clock_frequency 2500.0 output_datarate 5000.0 set_enable_fractional 0 set_auto_reference_clock_frequency 100.0 select_manual_config false set_m_counter 50 set_ref_clk_div 1 set_l_counter 2 set_power_mode 1_1V enable_mcgb 0 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 0 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 0 mcgb_in_clk_freq 2500.0 mcgb_out_datarate 5000.0 enable_bonding_clks 0 pma_width 64 set_parameter_list L-Counter,M-Counter,N-Counter,C-Counter,K-Counter,PLL output datarate,PLL output frequency,VCO frequency,PFD frequency,C0 Counter Output Frequency,C0 Counter Output Frequency in Hz,C1 Counter Output Frequency,C1 Counter Output Frequency in Hz set_parameter_values 1,1,1,1,0,5000.0,2500.0,1250.0,1250.0,0,0,0,0 set_display_units ,,,,,Mbps,MHz,MHz,MHz,ps,ps,ps,ps deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pcie_s10_hip_ast_0_lcpll_g3xn

altera_pcie_s10_hip_ast_altera_xcvr_atx_pll_s10_htile v23.0.0

Parameters rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 set_capability_reg_enable 0 set_user_identifier 160 set_csr_soft_logic_enable 0 rcfg_file_prefix altera_xcvr_atx_pll_s10 rcfg_sv_file_enable 0 rcfg_h_file_enable 0 rcfg_mif_file_enable 0 rcfg_multi_enable 0 set_rcfg_emb_strm_enable 0 rcfg_reduced_files_enable 0 rcfg_profile_cnt 2 rcfg_profile_select 1 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data7 message_level error prot_mode PCIe Gen 3 bw_sel high refclk_cnt 1 refclk_index 0 primary_pll_buffer GX clock output buffer enable_8G_path 0 enable_28G_output_frm_abv_atx 0 enable_28G_output_frm_blw_atx 0 enable_28G_local_atx_path 0 enable_28G_input_frm_abv_atx 0 enable_28G_input_frm_blw_atx 0 enable_GXT_out_buffer_abv 0 enable_GXT_out_buffer_blw 0 enable_GXT_clock_source disabled enable_pcie_clk 1 enable_atx_to_fpll_cascade_out 0 set_output_clock_frequency 4000.0 output_clock_datarate 8000.0 set_auto_reference_clock_frequency 100.0 select_manual_config false m_counter 40 ref_clk_div 1 l_counter 2 usr_analog_voltage 1_1V enable_mcgb 1 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 1 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 1 mcgb_in_clk_freq 4000.0 mcgb_out_datarate 8000.0 enable_bonding_clks 1 pma_width 32 gui_parameter_list L cascade predivider/VCO divider(valid in cascade mode) ,L counter (valid in non-cascade mode),L cascade counter (valid in cascade mode),M counter,K counter (valid in fractional mode),N counter,PLL output frequency,vco_freq,datarate gui_parameter_values select_div_by_2,1,1,8,0,1,2500 MHz,0 MHz,0 Mbps deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

pcie_s10_hip_ast_0_lcpll_g3xn_lcpll_g3xn

altera_xcvr_atx_pll_s10_htile v19.1.1

Parameters rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 set_capability_reg_enable 0 set_user_identifier 160 set_csr_soft_logic_enable 0 rcfg_file_prefix altera_xcvr_atx_pll_s10 rcfg_sv_file_enable 0 rcfg_h_file_enable 0 rcfg_mif_file_enable 0 rcfg_multi_enable 0 set_rcfg_emb_strm_enable 0 rcfg_reduced_files_enable 0 rcfg_profile_cnt 2 rcfg_profile_select 1 rcfg_profile_data0 rcfg_profile_data1 rcfg_profile_data2 rcfg_profile_data3 rcfg_profile_data4 rcfg_profile_data5 rcfg_profile_data6 rcfg_profile_data7 message_level error prot_mode PCIe Gen 3 bw_sel high refclk_cnt 1 refclk_index 0 primary_pll_buffer GX clock output buffer enable_8G_path 0 enable_28G_output_frm_abv_atx 0 enable_28G_output_frm_blw_atx 0 enable_28G_local_atx_path 0 enable_28G_input_frm_abv_atx 0 enable_28G_input_frm_blw_atx 0 enable_GXT_out_buffer_abv 0 enable_GXT_out_buffer_blw 0 enable_GXT_clock_source disabled enable_pcie_clk 1 enable_atx_to_fpll_cascade_out 0 set_output_clock_frequency 4000.0 output_clock_datarate 8000.0 set_auto_reference_clock_frequency 100.0 select_manual_config false m_counter 40 ref_clk_div 1 l_counter 2 usr_analog_voltage 1_1V enable_mcgb 1 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 1 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 1 mcgb_in_clk_freq 4000.0 mcgb_out_datarate 8000.0 enable_bonding_clks 1 pma_width 32 gui_parameter_list L cascade predivider/VCO divider(valid in cascade mode) ,L counter (valid in non-cascade mode),L cascade counter (valid in cascade mode),M counter,K counter (valid in fractional mode),N counter,PLL output frequency,vco_freq,datarate gui_parameter_values select_div_by_2,1,1,8,0,1,2500 MHz,0 MHz,0 Mbps deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)