Argus (Vision on FPGAs)
OverviewAdvances in deep learning have led to the widespread use of convolutional neural networks (CNNs) for solving the most challenging computer vision problems. However, the high computational intensity of CNNs is beyond the capability of general-purpose CPUs, requiring specialized hardware acceleration; In particular, FPGAs have been shown effective for CNNs. Argus is a project that aims to create more efficient FPGA-based CNN accelerators by suggesting novel ideas.
- Argus: An End-to-End Framework for Accelerating CNNs on FPGAs (IEEE Micro): Argus project overview.
- Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer (FCCM'17): Minimizes memory bandwidth requirements by balancing input and weight data transfers.
- Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces (FPL'18): Develops a memory interconnect for DNN accelerator interfaces, which tend to comprise many narrow ports, and FPGA DRAM controller interfaces, which tend to be wide buses.
- Overcoming Resource Underutilization in Spatial CNN Accelerators (FPL'16) and Maximizing CNN Accelerator Efficiency Through Resource Partitioning (ISCA'17): Partitions FPGA resources into multiple CNN layer processors (CLPs) to achieve near-perfect dynamic arithmetic unit utilization.
- Fused-Layer CNN Accelerators (MICRO'16): Describes a mechanism to process adjacent CNN layers in a way that supports caching of intermediate inter-layer data, dramatically reducing the total off-chip memory transfer.
Online CNN Verilog Generator
Argus is an end-to-end framework for accelerating CNNs on FPGAs. The core of Argus is an accelerator generator that translates high-level CNN descriptions into efficient multi-core accelerator designs. Argus explores an extensive design space, jointly optimizing all design aspects for the target FPGA and generating multi-core accelerator designs that achieve near-perfect dynamic arithmetic unit utilization.
To minimize user effort, Argus includes a model parser for importing CNN models from popular machine learning frameworks and a software stack for running an FPGA-backed CNN inference microservice. Contact Zavosh Mottahedeh <firstname.lastname@example.org> to request support for additional CNN models or FPGA platforms or if you find any problems with the generated designs.