Modern DRAM chips provide power management features to help meet the increasing demand for energy in computing. The power management policies are set via the memory controller. The goal of the project is to understand the basis of these policies at an architectural level. Based on this knowledge, we aim to build a kernel which can assist in energy efficient computing.

We have investigated architectural details of memory addressing schemes for Intel SandyBridge and their relation to power management; We intend to integrate this information to kernel’s memory management sub-system so that the page-allocation decisions are aligned to hardware boundaries, and over which power control can be exercised judiciously. We are also exploring the possibility of putting the idle memory devices at various level of granularity to deeper sleep states (possibly power gating) to maximize power savings

Latest Updates


  • Identitication and Validation of address mapping Schemes for Intel SandyBridge Platforms, Xeon E5-2600 and Xeon 5500. We have used Intel PCM tools available for verification of the address mapping schemes here


  • Documentation available on Address Mapping Scheme and Power saving Options for SandyBridge here


Sample Result


Our measurements show that we achieved up to 22% energy savings for certain workloads. The extent of savings can be further increased by the possibility of having deeper low power memory states.




  • Exploring and develop software techniques for enabling deeper low power memory states under low load conditions


  • Re-design the kernel’s mm subsystem to introduce the notion of hardware zones. Previous work on arm-mobile platforms can provide good insight here. Here are some constructive criticism on the design here


  • Address mapping tables changing at run-time due to events like hot-plug as well as due to adaptive paging policies in the memory controller can act as design challenges.



  • Code for Address Mapping Tables, Specific to Intel Platform[Mbox driver]



  • Module for  Rank-Wise Memory Traffic Generator [MemTraffic]




  • Saptarshi Sen, Advanced Project Report, CSE 523-524, 2013, Compas Lab, Stony Brook University Dark Memory Rev 1.0