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20.7   Other PCI Features

20.7.1   Master Abort

Accesses that pass a host-to-PCI bridge, or a PCI-to-PCI bridge, but have a non-mapped address as target will call the master abort handling in the bridge. This is implemented in Simics using the bridge mapping, where the most recent bridge will be called signaling that the access wasn't claimed by any device. The bridge can then perform the appropriate master abort semantics, and return a Sim_PE_No_Exception pseudo exception. If a PCI device issues a transaction on the local bus that is not claimed by any device, the memory-space access will return the pseudo exception Sim_PE_IO_Not_Taken directly to the device. This is the same exception that the bridge will get in case of a bridge mapping. It is important to use bridge mappings for PCI memory-spaces, since the processor should not get the Sim_PE_IO_Not_Taken exception on accesses, but instead get informed by the bridge about the error.

20.7.2   Target Abort

A PCI device can signal a target abort by returning the Sim_PE_IO_Error pseudo exception on accesses. It should also be prepared to receive this error when doing memory accesses itself on the PCI bus. PCI bridges implemented in Simics may receive the Sim_PE_IO_Error exception from the PCI_BRIDGE interface if the access was done through a bridge mapping, for example a CPU-initiated access to a PCI device below the bridge.

20.7.3   Message Signaling Interrupt

There is no generic support in Simics for Message Signaling Interrupts (MSI). This is something that can be implemented on a per device (or bridge) basis.

20.7.4   Special Cycles

The PCI system in Simics does support PCI Special Cycles. However, most PCI bridges and devices modeled do not have Special Cycles support implemented.

20.7.5   System Error (SERR#)

System Error is used in PCI to signal unrecoverable errors. A PCI device can assert the SERR# line on the PCI bus upon errors, and the host-to-PCI bridge informs the Operating System of the error. System Error is supported by the PCI system in Simics, but not all modeled bridges and devices implement it.

20.7.6   Parity Error (PERR#)

Simics currently does not support PCI Parity Error signaling. Please contact Virtutech if you need this modeled.

20.7.7   Interrupt Acknowledge

Interrupt Acknowledge is a rarely used feature of PCI. It is implemented in Simics's pci-bus object, but most bridges and devices do not support it.

20.7.8   VGA Palette Snooping

Simics currently does not support VGA Palette Snooping. Please contact Virtutech if you need this modeled.

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