Previous - Up - Next

18.7   Understanding g-cache Statistics

The following statistics are available in a g-cache:

Total number of transactions

Count of all transactions received by the cache, including all transactions listed below.

Device data read/write

Number of transactions, e.g., DMA transfers, performed by devices against the memory-space to which the cache is connected. Device accesses are otherwise ignored by the cache and passed as-is to the next level cache.

Uncacheable data read/write, instruction fetch

Number of uncacheable transactions performed by the processor. Uncacheable transactions are otherwise ignored by the cache and passed as-is to the next level cache.

Data read transactions

Cacheable read transactions counted by the cache.

Data read misses

Cacheable read transactions that missed in the cache.

Data read hit ratio

1 − (cacheable read misses / cacheable read transactions)

Instruction fetch transactions

Cacheable instruction fetch transactions counted by the cache.

Instruction fetch misses

Cacheable instruction fetch transactions that missed in the cache.

Instruction fetch hit ratio

1 − (cacheable instruction fetch misses / cacheable instruction fetch transactions)

Data write transactions

Cacheable write transactions counted by the cache.

Data write misses

Cacheable write transactions that missed in the cache. This is not directly related to the number of transactions sent to the next level cache, which also depends on the write allocation and write-back policies selected for the cache.

Data write hit ratio

1 − (cacheable write misses / cacheable write transactions)

Copy-back transactions

Copy-back transactions performed by the cache to flush modified cache lines.

Previous - Up - Next