Medusa: A Scalable Memory Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces

Shen, Yongming; Ji, Tianchu; Ferdman, Michael; Milder, Peter

by Yongming Shen, Tianchu Ji, Michael Ferdman, Peter Milder

Reference:

Medusa: A Scalable Memory Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces Yongming Shen, Tianchu Ji, Michael Ferdman, Peter Milder, In 28th International Conference on Field Programmable Logic and Applications (FPL), 2018.

Bibtex Entry:

@inproceedings{ferdman-fpl-medusa-scalable-memory-interconnect-for-many-port-dnn-accelerators-and-wide-dram-controller-interfaces,
  title={Medusa: A Scalable Memory Interconnect for Many-Port {DNN} Accelerators and Wide {DRAM} Controller Interfaces},
  author={Yongming Shen and Tianchu Ji and Michael Ferdman and Peter Milder},
  booktitle={28th International Conference on Field Programmable Logic and Applications ({FPL})},
  year={2018},
  organization={IEEE},
  pdf={https://compas.cs.stonybrook.edu/%7Emferdman/downloads.php/FPL18_Medusa_Scalable_Memory_Interconnect_for_Many_Port_DNN_Accelerators_and_Wide_DRAM_Controller_Interfaces.pdf}
}