Shenghsun Cho shencho (at) cs.stonybrook.edu Resume

I am a Ph.D. from the Computer Architecture Lab at Stony Brook University. Currently I am working at Microsoft Azure as a Software Engineer, specialized in hardware/software integration and performance optimization. I have a broad interest in the field of computer architecture and operating systems, including FPGA reconfigurable computing, heterogeneous multicore systems, hardware accelerators, and network processing.

During my Ph.D. I was advised by Professor Mike Ferdman, focusing on memory systems, host-accelerator integration, and FPGA-based accelerators for datacenters.

• Ph.D. in Computer Science, Stony Brook University, NY, U.S.A., 2021
• M.S. in Electrical Engineering, National Taiwan University, Taiwan. 2007.
• B.S. in Computer Science and Information Engineering, National Central University, Taiwan. 2005.

• Software Engineer in cloud computing, Microsoft, Jun. 2021 - present

• Co-Op in software development, AMD Research, Mar. 2018 - Aug. 2018
• MPI software development
• Next-gen interconnect device driver

• Intern in FPGA hardware development, Microsoft Research, Jun. 2015 - Aug. 2015
• OpenCL high-level synthesis for FPGAs
• Multi-FPGA communication for cloud computing

• Senior Engineer in digital design and embedded software, Global Unichip Inc., Oct. 2007 - Jun. 2013
• Embedded software development
• ARM SoC architecture development
• High-speed interface digital design (USB 3.0, LVDS, V-By-One)

• Practical Model Checking on FPGAs [ACM]
  Shenghsun Cho, Mrunal Patel, Michael Ferdman, Peter Milder, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 14, Issue 2J, July 2021.

• Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments [PDF]
  Shenghsun Cho, Han Chen, Sergey Madaminov, Michael Ferdman, Peter Milder, in 47th International Symposium on Computer Architecture (ISCA), 2020.

• Taming the Killer Microsecond [PDF]
  Shenghsun Cho, Amoghavarsha Suresh, Tapti Palit, Michael Ferdman, Nima Honarmand, in 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018.

• FPGASwarm: High Throughput Model Checking on FPGAs [PDF]
  Shenghsun Cho, Michael Ferdman, Peter Milder, in 28th International Conference on Field Programmable Logic and Applications (FPL), 2018.

• A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs [PDF]
  Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter Milder, in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2018.

Full List

• Instructions for Performing Multi-Line Memory Accesses
  David A. Roberts, Shenghsun Cho, US Patent 11,023,410

• Dynamic virtualized field-programmable gate array resource control for performance and reliability
  David A. Roberts, Shenghsun Cho, US Patent 10,447,273

• Method and system for packet classification with reduced memory space and enhanced access speed
  Shenghsun Cho, Sheng-De Wang, US Patent 7,953,082

(Updated: Apr. 2023)