About Me
I am a Computer Science Ph.D. graduate from the Computer Architecture Lab at Stony Brook University. My research interests span computer architecture and operating systems, with particular focus on FPGA reconfigurable computing, heterogeneous multicore systems, hardware accelerators, and network processing.
During my doctoral studies, I was advised by Professor Mike Ferdman, where my research concentrated on memory systems, host-accelerator integration, and FPGA-based accelerators for datacenter applications.
Education
Ph.D. in Computer Science
Dissertation: Minimizing the Impact of Communication Latency between CPUs, Memory, and Accelerators
M.S. in Electrical Engineering
Thesis: A Packet Classification Architecture with Low Storage Requirements
B.S. in Computer Science and Information Engineering
Professional Experience
Software Engineer in Azure Cloud/AI
- Hardware/software integration and performance optimization.
- AI agent development.
Intern in Software Development
- MPI software development.
- Next-gen interconnect device driver development.
Intern in FPGA Hardware Development
- OpenCL high-level synthesis for FPGAs.
- Multi-FPGA communication for cloud computing.
Senior Engineer in Digital Design and Embedded Software
- ARM SoC architecture development.
- Embedded software development.
- High-speed interface digital design (e.g., USB 3.0, LVDS, V-By-One).
Publications (selected)
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Practical Model Checking on FPGAs [ACM]
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 14, Issue 2J, July 2021
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Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments [ACM]
in 47th International Symposium on Computer Architecture (ISCA), 2020
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Taming the Killer Microsecond [IEEE]
in 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018
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FPGASwarm: High Throughput Model Checking on FPGAs [IEEE]
in 28th International Conference on Field Programmable Logic and Applications (FPL), 2018
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A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs [ACM]
in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2018
Patents
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Instructions for Performing Multi-Line Memory Accesses
US Patent 11,023,410
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Dynamic virtualized field-programmable gate array resource control for performance and reliability
US Patent 10,447,273
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Method and system for packet classification with reduced memory space and enhanced access speed
US Patent 7,953,082
Contact
Email: shencho (at) cs.stonybrook.edu