Shenghsun Cho Ph.D. Candidate Computer Science Department Stony Brook University shencho (at) cs.stonybrook.edu CV

I am a PhD candidate in the Department of Computer Science at Stony Brook University, working with professor Mike Ferdman in the COMPAS Lab. I have a broad interest in the field of computer architecture and operating systems, including reconfigurable computing, heterogeneous multicore systems, and network processing. Currently I am doing research related to FPGA-based accelerators, focusing on host-accelerator integration and accelerator programming models.

• Ph.D. Candidate in Computer Science, Stony Brook University, NY, USA.
• M.S. in Electrical Engineering, National Taiwan University, Taiwan. 2007.
• B.S. in Computer Science and Information Engineering, National Central University, Taiwan. 2005.

• Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments [PDF]
  Shenghsun Cho, Han Chen, Sergey Madaminov, Michael Ferdman, Peter Milder, in 47th International Symposium on Computer Architecture (ISCA), 2020.

• Runtime-Programmable Pipelines for Model Checkers on FPGAs [PDF]
  Mrunal Patel, Shenghsun Cho, Michael Ferdman, Peter Milder, in 29th International Conference on Field Programmable Logic and Applications (FPL), 2019. (best paper candidate)

• Taming the Killer Microsecond [PDF]
  Shenghsun Cho, Amoghavarsha Suresh, Tapti Palit, Michael Ferdman, Nima Honarmand, in 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018.

• FPGASwarm: High Throughput Model Checking on FPGAs [PDF]
  Shenghsun Cho, Michael Ferdman, Peter Milder, in 28th International Conference on Field Programmable Logic and Applications (FPL), 2018.

• A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs [PDF]
  Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter Milder, in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2018.

• Dynamic virtualized field-programmable gate array resource control for performance and reliability
  David A. Roberts, Shenghsun Cho, US Patent 10,447,273

• Method and system for packet classification with reduced memory space and enhanced access speed
  Shenghsun Cho, Sheng-De Wang, US Patent 7,953,082

• Co-Op in software development, AMD Research, Mar. 2018 - Aug. 2018
• MPI software development
• Next-gen interconnect device driver

• Intern in FPGA hardware development, Microsoft Research, Jun. 2015 - Aug. 2015
• OpenCL high-level synthesis for FPGAs
• Multi-FPGA communication for cloud computing

• Senior Engineer, Global Unichip Inc., Oct. 2007 - Jun. 2013
• Embedded software development
• ARM SoC architecture development
• High-speed interface digital design (USB 3.0, LVDS, V-By-One)

(Updated: Jun. 2020)