I am an Assistant Professor in the Computer Science Department of Stony Brook University, where I co-direct the Computer Architecture Stony Brook (COMPAS) Lab. My general field of research is computer system design, emphasizing parallel computer architecture and operating systems.

I did my Ph.D. under the supervision of Josep Torrellas, in the i-acoma group of the CS Department of University of Illinois at Urbana-Champaign. For my Ph.D., I worked on various aspects of "Record and Deterministic Replay" of parallel programs on multi-processor systems in order to make parallel programming easier.

I am looking for motivated and hard-working students to work with me. If you are a new PhD student at Stony Brook and are interested in systems research, please send me an email to arrange an appointment.

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• Y. Duan, N. Honarmand and J. Torrellas, Asymmetric Memory Fences: Optimizing Both Performance and Implementability, in Proc. ASPLOS 2015. [PDF]


• N. Honarmand and J. Torrellas, Replay Debugging: Leveraging Record and Replay for Program Debugging, in Proc. ISCA 2014. [ACM][PDF]


• N. Honarmand and J. Torrellas, RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors, in Proc. ASPLOS 2014. [ACM][PDF]


• G. Pokam, K. Danne, C. Pereira, R. Kassa, T. Kranich, S. Hu, J. Gottschlich (Intel), N. Honarmand, N. Dautenhahn, S.T. King and J. Torrellas (UIUC), QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs, in Proc. ISCA 2013. [ACM][PDF]


• N. Honarmand, N. Dautenhahn, J. Torrellas, S.T. King, G. Pokam and C. Pereira, Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism, in Proc. ASPLOS 2013. [ACM][PDF]


• Robert Bocchino, Stephen Heumann, Nima Honarmand, Rakesh Komuravelli, Jeffrey Overbey, Patrick Simmons, Hyojin Sung, Mohsen Vakilian, Sarita V. Adve, Vikram S. Adve, Danny Dig and Marc Snir, A Language for Deterministic-by-Default Parallel Programming, Technical Report, Department of Computer Science, University of Illinois at Urbana Champaign, 2011. [PDF]


• B. Choi, R. Komuravelli, H. Sung, R. Smolinski, N. Honarmand, S. Adve, V. Adve, N. Carter and C. Chou, DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism, in Proc. PACT 2011 (Best Paper). [ACM][PDF]


• R. Bocchino, S. Heumann, N. Honarmand, S. Adve, V. Adve, A. Welc and T. Shpeisman, Safe Nondeterminism in a Deterministic-by-Default Parallel Language, in Proc. POPL 2011. [ACM][PDF]


• N. Honarmand, H. Sohofi, M. Abbaspour and Z. Navabi, APDL: A Processor Description Language for Design Space Exploration of Embedded Processors, in Proc. FDL 2007. [DBLP][PDF]


• N. Honarmand, A. Shahabi and Z. Navabi, A Heuristic Search Algorithm for Re-routing of On-Chip Networks in the Presence of Faulty Links and Switches, in Proc. EWDTS 2007. [PDF]


• N. Honarmand, H. Sohofi, M. Abbaspour and Z. Navabi, Processor Description in APDL for Design Space Exploration of Embedded Processors, in Proc. EWDTS 2007. [PDF]


• A. Shahabi, N. Honarmand and Z. Navabi, Programmable Routing Tables for Degradable Mesh-Based Networks on Chips, in Proc. Iranian Conference on Electrical Engineering 2007. [PDF]


• A. Shahabi, N. Honarmand and Z. Navabi, Programmable Routing Tables for Degradable Torus-Based Networks on Chips, in Proc. ISCAS 2007. [IEEE][PDF]


• N. Honarmand, A. Shahabi, H. Sohofi, M. Abbaspour, and Z. Navabi, High Level Synthesis of Degradable ASICs Using Virtual Binding, in Proc. VTS 2007 (Best Paper Candidate). [IEEE][PDF]


• A. Shahabi, N. Honarmand, H. Sohofi and Z. Navabi, Degradable Mesh-Based On-Chip Networks Using Programmable Routing Tables, IEICE Electronics Express, vol. 4, no. 10, May 2007. [IEICE][PDF]


• N. Honarmand and A. Afzali-Kusha, Low Power Combinational Multipliers using Data-driven Signal Gating, in Proc. APCCAS 2006. [IEEE][PDF]


• N. Honarmand, M.R. Javaheri, N. Sedaghati-Mokhtari and A. Afzali-Kusha, Power Efficient Sequential Multiplication Using Pre-computation, in Proc. ISCAS 2006. [IEEE][PDF]