Support for several processors talking to one cache is integrated in g-cache. You just need to specify the list of CPUs connected to the cache in the cpus attribute. Note that it is possible for the cache to use the STCs as described above even with several processors.
You can use the sample MESI protocol to connect several caches in a multiprocessor system. You need to provide the cache with a list of the other caches snooping on the bus using the snoopers attribute. If you have higher-level caches that are not snooping on the bus, you need to set the higher_level_caches attribute so that invalidation is done properly. Note that the sample MESI protocol was written to handle simple cases such as several L1 write-through caches with L2 caches synchronizing via MESI. To model more complex protocol, you will need to modify g-cache.
If you use LRU replacement with several processors, you may have problems with the way Simics schedules processor execution (read the chapter 17 for more information). You may want to lower the CPU switch time from its default value to prevent accesses "in the future" from changing the way LRU replacement is behaving.