Hello, I’m Tianchu Ji (冀天初), a PhD student studying Computer Architecture at Stony Brook University. I currently focus on optimization and automatic generation of FPGA-based Deep Learning accelerators.
I have been studying building hardware accelerator for LSTM models for better on-chip resource efficiency, lower latency and higher throughput. I have also helped build Medusa (our Scalable memory interconnect for many-port DNN accelerators) and a High Resolution Time-to-Digital Converter on FPGA. I am now focusing on exploring the sparsity of the Multihead-Attention-based Deep Learning models and seeking for the chances to accelerate the computation by using FPGA. You may download my resume here.
I’m living in the Long Island with my cat, Avery. When I’m free (which is rare), I write blogs and short stories in Chinese here.