Fall 2015 :: CSE 610 - Parallel Computer Architectures

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Due Dates

Unless stated otherwise, all deadlines are set to 11:59 PM of the respective due date.

Date	What
09/16	Project proposal due
09/30	Seminar topic due
10/26	Project midterm report deadline
12/01 & 12/03	Project presentations (in class)
12/16	Project final report due

Lectures Schedule

Date	What	Notes
08/25	No Class
08/27	Introduction	Book Chapter(s): Parallel Computer Architecture: A Hardware/Software Approach, Chapter 1.
09/01	Parallel Computing Basics	Reading(s): The Task of the Referee, by Smith. Amdahl’s Law in the Multicore Era, by Hill and Marty. The Landscape of Parallel Computing Research: A View from Berkeley, by Asanovic et al. The Future of Microprocessors, by Borkar and Chien. Hardware Trends: Challenges and Opportunities in Distributed Computing by Harris. Software and the Concurrency Revolution, by Sutter and Larus. Cost-Effective Parallel Computing, by Wood and Hill. Book Chapter(s): Parallel Computer Architecture: A Hardware/Software Approach, Chapter 1.
09/03
09/08	No Class (University Break)
09/10	Shared Memory Basics	Reading(s): How to make a multiprocessor computer that correctly executes multiprocess programs, by Lamport. Shared Memory Consistency Models: A Tutorial, by Adve and Gharachorloo. Foundations of the C++ concurrency memory model, by Boehm and Adve. The Java memory model, by Manson et al. Book Chapter(s): H&P, Chapter 4. Parallel Computer Architecture: A Hardware/Software Approach, Chapter 5. A Primer on Memory Consistency and Cache Coherence, Chapters 1-3.
09/15
09/17
09/22	Cache Coherence	Reading(s): A Survey of Cache Coherence Schemes for Multiprocessors, by Stenstrom. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus, by Sweazey and Smith. Starfire: Extending the SMP Envelope, by Charlesworth. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor, by Lenoski et al. Performance Optimizations, Implementation, and Verification of the SGI Challenge Multiprocessor, by Galles and Williams. Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol, by Sorin et al. So Many States, So Little Time: Verifying Memory Coherence in the Cray X1, by Abts et al. Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes, by Gupta et al. Cache Invalidation Patterns in Shared-Memory Multiprocessors, by Gupta and Weber False Sharing and Spatial Locality in Multiprocessor Caches, by Torrellas et al. Book Chapter(s): Parallel Computer Architecture: A Hardware/Software Approach, Chapters 6 & 8. A Primer on Memory Consistency and Cache Coherence, Chapters 6-9.
09/24
09/29
10/01
10/06
10/08	Shared-Memory Synchronization	Reading(s): Efficient Synchronization Primitives for Large-Scale Cache-Coherent Multiprocessors, by Goodman et al. Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors, by Mellor-Crummey and Scott. Efficient Synchronization: Let Them Eat QOLB, by Kägi et al. Synchronization and Communication in the T3E Multiprocessor, by Scott. Book Chapter(s): Shared-Memory Synchronization, Chapters 1-5 & 7.
10/13
10/15
10/20	No Class (CEWIT Conference)
10/22	Memory Consistency Models	Reading(s): Shared Memory Consistency Models: A Tutorial, by Adve and Gharachorloo. Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors, by Gharachorloo et al. Two Techniques to Enhance the Performance of Memory Consistency Models, by Gharachorloo et al. An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors, by Pai et al. Threads Cannot Be Implemented As a Library, by Boehm. Book Chapter(s): A Primer on Memory Consistency and Cache Coherence, Chapters 3-5.
10/27
10/29
11/03
11/06	Guest lecture by Prof. Wenisch, University of Michigan
11/10	Interconnection Networks	Reading(s): The Alpha 21364 Network Architecture, by Mukherjee et al. On-Chip Interconnection Architecture of the Tile Processor, by Wentzlaff et al. Flattened Butterfly : A Cost-Efficient Topology for High-Radix Networks, by Kim et al. The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus, by Scott and Thorson. Microarchitecture of a High-Radix Router, by Kim et al. SeaStar Interconnect: Balanced Bandwidth for Scalable Performance, by Brightwell et al. The Gemini System Interconnect, by Alverson et al. Book Chapter(s): High Performance Datacenter Networks: Architectures, Algorithms, and Opportunities, All Chapters (It's a short synthesis lecture). On-Chip Networks, Chapters 2, 5 & 6. Principles and Practices of Interconnection Networks, the whole book (highly recommended).
11/12
11/17
11/19
11/24
11/26	No Class (Thanksgiving Break)
12/01	Vector, SIMD and SIMT Processing	Reading(s): The Cray-1 Computer System, by Cray Research, Inc. Tarantula: A Vector Extension to the Alpha Architecture, by Espasa et al. NVIDIA’s Next Generation CUDA Compute Architecture: Kepler GK110, by NVIDIA. NVIDIA GeForce GTX 980 Featuring Maxwell, The Most Advanced GPU Ever Made, by NVIDIA. Book Chapter(s): Computer Architecture: A Quantitative Approach (5th Ed), Chapter 4 and Appendix G.
12/03